Unexpected Behavior with Continuous Read Mode on AD4112

I'm trying to perform a continuous read of four channels on the AD4112 as described on page 35 of the datasheet. I have channels 0, 1, 2, and 3 configured and enabled with different combinations of single ended and differential voltage mux inputs along with different filter configurations. When I perform four sequential single conversions, I get the results I expect. However, if I try to use the Continuous Read mode, it appears that the 4112 only converts channel 1 continuously. I have verified this by examining the data being returned, measuring the conversion time, and setting DATA_STAT in the INTERFACE register to append the status byte to the reading. I have also confirmed that my logic analyzer trace is identical to Figure 55.

So, I'm stumped. I was hoping to offload the collection of ADC data using a DMA channel on my uP but until this gets resolved, I have to collect it one conversion at a time using interrupts. 



Clarified mitigation.
[edited by: WallyBalls at 12:28 PM (GMT -5) on 27 Dec 2020]
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  • 0
    •  Analog Employees 
    on Dec 28, 2020 1:04 AM

    Hi,

    You have mentioned that you get a valid results in continuous conversion mode? Is that correct? and you just add the continuous read mode Is that right?

    In continuous read mode, conversions are placed on the DRDY line automatically and there is no need to issue a read data register instruction. However, in continuous read mode, the data register is updated each time a conversion is read. So, if you have a slow SCLK, you may read some of the current conversion and some bits of the next conversion, leading to an overall invalid reading. In continuous read mode, you need to ensure that each conversion read is completed before the next conversion is available.

    Can you share us a scope shot of your interface in continuous read mode? and also your ADC register map settings?

    Thanks,

    Jellenie

  • No, I get valid results in Single Read mode if I have 4 channels enabled and perform a read each time the MISO/RDY goes low.

    Yes, I understand how Continuous Read mode works and I understand that the data register will be overwritten if I don't collect the data fast enough.

    Here is my STM32 code. This is a piece of test code where I basically set up the ADC for continuous read mode and write each value to a buffer when RDY goes low. With 4 channels enabled I only see one channel being converted continuously. 

    #define ADCCLK 0x0C
    
    void startSINGLE(void)
    {
    k=0
    N=0;
      for (k=0; k<8; k++)
      {
      temp=getADC16(CHAN0+k);
      chanPEEK[k]=temp;
      if ((temp & 0x8000)==0x8000)
      N+=1;
    }
    if (N>0)
    {
      if (N>1)
        writeADCREG16(ADCMODE, 0x0000+A2DCLK);
      else
        writeADCREG16(ADCMODE, 0x2000+A2DCLK);
      writeADCREG16(INTERFACE, 0x00C0); // add status byte to end of output and enable continuous read
      HAL_GPIO_WritePin(A2D_CS_GPIO_Port, A2D_CS_Pin, GPIO_PIN_RESET); // lower CS pin to ADC
      while(1)
      {
        irq=HAL_GPIO_ReadPin(A2D_IRQ_GPIO_Port, A2D_IRQ_Pin);
        if (irq==GPIO_PIN_RESET) 
        {
             HAL_SPI_Receive(&hspi1, (uint8_t*)aRxBuffer, 4, 5000);
    
        }
    }

  • 0
    •  Analog Employees 
    on Jan 4, 2021 2:10 AM in reply to WallyBalls

    Hi, 

    Apologies. I cannot reproduce this as I am currently working from home. I'll let you know if we get a chance. 

    Thanks,

    Jellenie

  • 0
    •  Analog Employees 
    on Jan 4, 2021 2:26 AM in reply to WallyBalls

    Hi, 

    Actually this should not be required. May I know what is your input range? bipolar coding can be used to represent both negative and positive differential voltages applied to the analog inputs of the ADC. So that should not be an issue if the ADC is configured in bipolar mode. 

    Thanks,

    Jellenie

  • I completely agree with your statement. But the fact is that I can't perform a continuous read of a Single Ended input unless I use Unipolar coding. Why not ask the designers in Ireland if they're aware of this?

  • 0
    •  Analog Employees 
    on Jan 4, 2021 3:39 AM in reply to WallyBalls

    Hi, 

    We haven't seen this issue before or in any of our Sigma Delta ADCs. So I presumed that there could be some other things in the hardware/software setup might have causing this issue other than the setting of the coding format. 

    Usually, when DOUT/RDY stops pulsing at any time and it stays high or low (even though the ADC is configured for continuous conversion mode), this indicates that the serial interface has become asynchronous (incorrect number of SCLK pulses, glitches on the SCLK line). Ensure that the correct number of SCLK pulses are being used for each read/write operation.

    I also recommended to tie DIN and SCLK high when they are not being used to prevent glitches affecting the SPI interface. When CS is low the interface is always waiting for a Falling edge of SCLK to indicate that a serial transaction is being written to the part. When it receives a falling edge it checks DIN, if DIN is high then it ignores the falling edge, if DIN is low then it expects a write to the communications register. Tying DIN high will mean any noise on SCLK will be ignored and tying SCLK high will make it less susceptible to noise and so makes a more robust serial interface.

    Though I really find it weird that the issue was solved upon setting the ADC in unipolar mode. May I know your analog and reference input voltage? And does your VINCOM connected to AVSS/GND? If it is okay, can you also share us your schematic? 

    Can you also check the following in both unipolar and bipolar mode. 

    1) stop reading back the conversions and just monitor the DOUT/RDY pin to determine if it is pulsing at the selected output data rate.

    2) Disable the continuous read function and then read the data register in standard continuous conversion mode. Is the value in the data register correct in both coding format?

    Thanks,

    Jellenie

  • Jellenie,

    I am using the AD4112 eval board (EVAL-AD4112SDZ)  so you have my schematic. My setup is:

    1) R37 is shorted so that +VA_ISO is 3.3V

    2) I have 5VDC connected to VIN0 and VCOM

    3) I am using the onboard reference

    Forcing the SPI clock high when not in use is a nontrivial task with the uP that I'm using. I need to start moving forward with my project and the experiments you are asking for will consume more time than I have. I really do believe I have found the solution to a HW bug in the chip and suggest you try the following experiment on your side: reset the chip and configure two channels - 1 single ended  on CHAN0 and 1 differential on CHAN1. Set them both up for bipolar coding and give them the same filter settings of SINC3 at 10SPS. Set CS low and send 0X00C0 to the IFMODE register to start continuous read with the status byte appended to the data. Capture the resulting data on the logic analyzer. You will see RDY go low every 200msec and, if you clock the data out, you will also see that this only occurs for CHAN1. In other words, the timing indicates that CHAN0 is being converted but that the AD4112 is net setting RDY when it is ready.

Reply
  • Jellenie,

    I am using the AD4112 eval board (EVAL-AD4112SDZ)  so you have my schematic. My setup is:

    1) R37 is shorted so that +VA_ISO is 3.3V

    2) I have 5VDC connected to VIN0 and VCOM

    3) I am using the onboard reference

    Forcing the SPI clock high when not in use is a nontrivial task with the uP that I'm using. I need to start moving forward with my project and the experiments you are asking for will consume more time than I have. I really do believe I have found the solution to a HW bug in the chip and suggest you try the following experiment on your side: reset the chip and configure two channels - 1 single ended  on CHAN0 and 1 differential on CHAN1. Set them both up for bipolar coding and give them the same filter settings of SINC3 at 10SPS. Set CS low and send 0X00C0 to the IFMODE register to start continuous read with the status byte appended to the data. Capture the resulting data on the logic analyzer. You will see RDY go low every 200msec and, if you clock the data out, you will also see that this only occurs for CHAN1. In other words, the timing indicates that CHAN0 is being converted but that the AD4112 is net setting RDY when it is ready.

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