Unexpected Behavior with Continuous Read Mode on AD4112

I'm trying to perform a continuous read of four channels on the AD4112 as described on page 35 of the datasheet. I have channels 0, 1, 2, and 3 configured and enabled with different combinations of single ended and differential voltage mux inputs along with different filter configurations. When I perform four sequential single conversions, I get the results I expect. However, if I try to use the Continuous Read mode, it appears that the 4112 only converts channel 1 continuously. I have verified this by examining the data being returned, measuring the conversion time, and setting DATA_STAT in the INTERFACE register to append the status byte to the reading. I have also confirmed that my logic analyzer trace is identical to Figure 55.

So, I'm stumped. I was hoping to offload the collection of ADC data using a DMA channel on my uP but until this gets resolved, I have to collect it one conversion at a time using interrupts. 

Clarified mitigation.
[edited by: WallyBalls at 12:28 PM (GMT -5) on 27 Dec 2020]
  • 0
    •  Analog Employees 
    on Dec 28, 2020 1:04 AM


    You have mentioned that you get a valid results in continuous conversion mode? Is that correct? and you just add the continuous read mode Is that right?

    In continuous read mode, conversions are placed on the DRDY line automatically and there is no need to issue a read data register instruction. However, in continuous read mode, the data register is updated each time a conversion is read. So, if you have a slow SCLK, you may read some of the current conversion and some bits of the next conversion, leading to an overall invalid reading. In continuous read mode, you need to ensure that each conversion read is completed before the next conversion is available.

    Can you share us a scope shot of your interface in continuous read mode? and also your ADC register map settings?



  • No, I get valid results in Single Read mode if I have 4 channels enabled and perform a read each time the MISO/RDY goes low.

    Yes, I understand how Continuous Read mode works and I understand that the data register will be overwritten if I don't collect the data fast enough.

    Here is my STM32 code. This is a piece of test code where I basically set up the ADC for continuous read mode and write each value to a buffer when RDY goes low. With 4 channels enabled I only see one channel being converted continuously. 

    #define ADCCLK 0x0C
    void startSINGLE(void)
      for (k=0; k<8; k++)
      if ((temp & 0x8000)==0x8000)
    if (N>0)
      if (N>1)
        writeADCREG16(ADCMODE, 0x0000+A2DCLK);
        writeADCREG16(ADCMODE, 0x2000+A2DCLK);
      writeADCREG16(INTERFACE, 0x00C0); // add status byte to end of output and enable continuous read
      HAL_GPIO_WritePin(A2D_CS_GPIO_Port, A2D_CS_Pin, GPIO_PIN_RESET); // lower CS pin to ADC
        irq=HAL_GPIO_ReadPin(A2D_IRQ_GPIO_Port, A2D_IRQ_Pin);
        if (irq==GPIO_PIN_RESET) 
             HAL_SPI_Receive(&hspi1, (uint8_t*)aRxBuffer, 4, 5000);

  • 0
    •  Analog Employees 
    on Dec 28, 2020 3:16 AM in reply to WallyBalls


    Apologies, I do not see other ADC configuration settings (i.e. Channel, Setup, etc.) in the above flow. The snippet is also not clear to me. I am not a programmer, however I just wanted to understand how it works. Are you monitoring the RDY pin? Is that irq connected to DRDY pin? 

    Please also take note that if you are in continuous read mode, you can no longer configure any registers in this mode. When the part is already in continuous read mode, the only serial interface operations possible are reads from the data register. The dummy read and the software reset are the only commands that the interface recognizes after it is placed in continuous read mode. So it is important to understand the complete flow of the code/program on where are the channels are being enabled to ensure that the ADC is properly configured before running in continuous read mode. 

    If you can also share us a scope shot of your digital interface then that would also be helpful. 



  • For the record, I'm using the EVAL-AD4112SDZ and attaching the SPI signals from an STM32 microprocessor to the pins on header J10. Here's the sequence of events and the data I'm writing to each register:

    1. Reset ADC by clocking 64 ones to DIN with CS low
    2. Wait 1 msec
    3. Write 0x2400 to GPIOCON to turn on the LEDs (this works)
    4. In a loop do the following for channels n=0-3:
      Write 0x1300 to SETUPCONn - bipolar coding, enabled, and external reference
      Write 0x8xxx  to CHn - equal to 0x8010, 0x9030, 0xA050, and 0xB070 for n=0-3
      Write 0x55567C to GAINn
      Write 0x800000 to OFFSETn
    5. Write 0x000C to ADC mode - use external crystal with Continuous Conversion
    6. Manually set CS low
    7. Write 0x00C0 to IFMODE - CONTREAD with status appended to data
    8. Start monitoring DOUT/RDY signal for falling edge

    Note that I am leaving the filters registers at their default value. Here is my logic analyzer output showing the complete sequence:

    And here is a detail of the last instruction going out to the IFMODE register:

    So that's it - 4 channels enabled, continuous read mode enabled but after 3 seconds the DOUT/RDY pin never goes low.

  • 0
    •  Analog Employees 
    on Dec 29, 2020 4:04 AM in reply to WallyBalls


    Thanks for these details. One more question, while monitoring DRDY pin, is your /CS high? When /CS is high, the DOUT/RDY pin is in high impedance state. Therefore, the DOUT/RDY pin will not indicate the end of the conversion. Can you confirm this as well please?