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AD4110 RDY

HI, I'm trying to figure this problem but i can't solve by myself. It's about /RDY. 

I know when /RDY(Data Ready Output) goes low, it indicates the completion of a conversion and ready to get conversion data.

Question 1. 

If I bring SYNC to high to start conversion, does it affect /RDY goes to low? 

Because uhm.. to complete a conversion(/RDY is low), It should start a conversion first(/SYNC is high).

Question 2. 

How can I decide to choose to get Serial Interface Read Sequence(Figure 69) or ADC_DATA Register (Figure 70)?

I know the sequence but I don't know which makes the /RDY state go high.

One is when SYNC is low, RDY is brought high.

Second is if data has not been read after conversion.

At the Second reason, Is Data means 24-BIT Conversion Register Data? 

Question 3.

What is next update? 

Thank you for replying. 

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  • Hi,

    1. Pg 12 explains that when \SYNC is brought low then ADC aborts any active conversion & \RDY is brought high if it is low and when \SYNC is brought high, starts new conversion after number of clock cycles. Only after the conversion, \RDY is pulled low.

    2. Yes, once the data (24-BIT Conversion Register Data) is ready, \RDY/DOUT is pulled low so that data can be read from the DUT.

    3. Next update means the next sample which is 24-BIT data.

    Thanks

    Regards

    Vikas Jeevannavar

Reply
  • Hi,

    1. Pg 12 explains that when \SYNC is brought low then ADC aborts any active conversion & \RDY is brought high if it is low and when \SYNC is brought high, starts new conversion after number of clock cycles. Only after the conversion, \RDY is pulled low.

    2. Yes, once the data (24-BIT Conversion Register Data) is ready, \RDY/DOUT is pulled low so that data can be read from the DUT.

    3. Next update means the next sample which is 24-BIT data.

    Thanks

    Regards

    Vikas Jeevannavar

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