I've been working with the AD7172-2 for almost two years now and it have been working.
I'm now redesigning the prototype board to fit the final product. Schematic is exactly the same and board layout around the AD7172-2 is almost exactly the same. The issue is the AD7172-2 does not communicate properly over SPI anymore. The software and communication have been working fine on the prototype board. I have tried three different chips(same batch), same problem.
What is happening is that after the reset (bunch of zeros) I read the ID register. During this read the MISO signal decides to change on the clock leading edge instead of falling edge at one bit. Same bit every time(not only in ID register; but other places also). I have checked and filtered all signals on the SPI interface and there is no strange spikes etc, it's very smooth and looks perfect. This is done with a 1Ga/s, 100mhz scope.....since timing T3 and T4 require a 25nS high of the clock I should be able to see if there was a problem.
Do you have any idea what could cause this?
The picture shows clock and MISO signal. This is the shift out of the ID register two bytes. The picture shows the end of the first byte and beginning of second byte. The arrow show where it shifts data at wrong clock edge.
I will answer myself here since I found the issue by a fluke. The problem was that my microcontroller ISP is interfaced on the same SPI lines. When running in debug mode it messed up the communication…
I will answer myself here since I found the issue by a fluke. The problem was that my microcontroller ISP is interfaced on the same SPI lines. When running in debug mode it messed up the communication.
Good to hear that you have solved this issue. However, we also have a Digital Interface FAQ for Sigma Delta ADC that you may find useful when dealing some issues with SPI communication. https://ez.analog.com/data_converters/precision_adcs/f/q-a/23871/digital-interface-faq---sigma-delta-adc