We have an AD7768 evaluation board and want to connect it to a Zedboard and use the HDL provided by Analog Devices. However, we're uncertain at the moment about what voltage we should set on the Zedboard for the FMC IO. The Zedboard can be configured for 1.8 V or 2.5 V by setting the jumper J18. It can also be set to 3.3 V but you have to solder a short for that.
The HDL constraints file, https://github.com/analogdevicesinc/hdl/blob/master/projects/ad7768evb/zed/system_constr.xdc , suggests that the FMC pins should be set at 2.5 V.
However, from the data sheet for the ADC chip and the circuit diagram for the ADC evaluation board it looks like the IO voltages levels at the FMC connector are set to 3.3 V. The following has been taken from the AD7768 data sheet:
IOVDD Digital Supply: This pin sets the logic levels for all interface pins.The circuit diagram of the evaluation board shows the IOVDD pin being driven from a 3.3V regulator (U16, sheet5), it is connected to the IOVDD pin 35 of the AD7768 chip (sheet 4).As the data out pins (DOUT0 to DOUT7) of the ADC chip are directly connected to the FMC-LPC connector (sheet 7) it could be assumed that the signals on the FMC-LPC connector of the ADC evaluation board are set to operate at 3.3V
We'd be very grateful for some guidance on this.
(Sorry to post this in two different subgroups. I initially posted it in the high speed ADCs one by mistake but had no replies there and after waiting a while I've posted here as well in case it got overlooked.)
Hi,As mentioned, the IOVDD on device works from 2.5V to 3.3V or 1.8V. The eval board uses 3.3V IOVDD supply and the SDP-H1 is configured to work for the same. Zedboard is configured to work at 2.5V.
In general, 2.5V logic levels work with 3.3V as well. Hence, in this case it would work fine just as it is. Just to be on safer side, please reconfigure it to 3.3V on zedboard and the constraints as well.
Thanks for your help, that's very useful. We'll reconfigure the Zedboard to 3.3 V and change the constraints as you suggest.