AD7124-4 CRC

Hi,

The checksum (8-bit CRC)  is appended at the end of each read and write transaction. All memory map read and write operations have a CRC check performed. So for example, when writing to a register, a CRC check failure results in the error flag being set and the write operation being aborted. However, to ensure that the register write was successful, read back the register and verify the checksum.

I think there's a section in the datasheet that discussed how CRC checksum is calculated for the read and write transaction. So ideally you are expecting something similar to the figures below. Can you share as a scope shot of your digital interface please?  

You can also check this sample code as I know this includes CRC computation.

https://wiki.analog.com/resources/tools-software/uc-drivers/ad7124 

If you have specific query regarding the no-OS driver for AD7124, I think someone from the Microcontroller no-OS Drivers community might be able to help you.

Thanks,

Jellenie

Hi,

The checksum (8-bit CRC)  is appended at the end of each read and write transaction. All memory map read and write operations have a CRC check performed. So for example, when writing to a register, a CRC check failure results in the error flag being set and the write operation being aborted. However, to ensure that the register write was successful, read back the register and verify the checksum.

I think there's a section in the datasheet that discussed how CRC checksum is calculated for the read and write transaction. So ideally you are expecting something similar to the figures below. Can you share as a scope shot of your digital interface please?  

You can also check this sample code as I know this includes CRC computation.

https://wiki.analog.com/resources/tools-software/uc-drivers/ad7124 

If you have specific query regarding the no-OS driver for AD7124, I think someone from the Microcontroller no-OS Drivers community might be able to help you.

Thanks,

Jellenie

Hi

Thank you so much for your time and consideration.

Actually, my problem was that I turned on the DATA_STATUS in ADC_Control regiuster so I expected the status register after the data.

However, in the case that the CRC SPI error is enabled, ADC doesn't send the satus register any more and CRC value replaces the status register.

Therefore, I read the CRC value just after finishing the data and read the status register separately.

Regards,  

Hi,

Actually you can still use the Data+status. You just need additional 8 SCLKs for your data corresponding to 32SCLKs data output. Then, the next 8SCLKs will be the CRC.

Thanks,

Jellenie