I want to implement simultaneous reading from AD7606 while writing to AD5761 DAC. Only channel 1 and 5 of AD7606 will be reading.
For that purpose I plan to use 2 SPI channels of ESP32 chip, one as master and one as slave.
Both ESP32 CSs connected together and wired to DAC’s SYNC and ADC’s CS.
So with the first 16 CLKs data from ADC channels 1 and 5 will be read, and at the same time first 16 of 24 bits will be sent to DAC. Then the CLK continue ticking thus finishing load DAC’s register with its 24 bit, and after that common CS go inactive. 2x8 bits pushed into MISOs from ADC are to be ignored.
Then the next CONVST pulse applied, followed by BUSY which loads ADC registers with new data that can be read with next 16 (24) CLKs.
Will that scheme work?
Yes, the AD7606 side of things seems alright. Note that after the 16th clock the AD7606 will start clocking out V2 in DOUTA and V6 in DOUTB, but you can ignore that data.
After the following BUSY…
Sorry, the AD5761 meant everywhere in the message
After the following BUSY falling edge, new V1 and V5 data will be clocked out again.