AD7124-8

Hello,

i am using AD7124-8 for processing 10 analog channel. Below the sequence of steps performed. When for the first time below sequence is executed, i am getting REF_DET_ERR (Reference detection. This flag indicates when the external reference being used by the ADC is open circuit or less than 0.7 V.) and surprisingly not getting REF_DET_ERR from second iteration.

1. Configure ADC Control register.

2. Configure Error enable register.

3. Configure all channel registers.

4. enable each channel and read data and error registers.

Could you please help me to understand this behaviour?

Thanks,

Kalyan

  • 0
    •  Analog Employees 
    on Oct 19, 2020 1:10 AM 1 month ago

    Hi,

    Can you send us your register map settings please?

    Can you also set the configuration register first before enabling error registers? Are you using internal or external reference?

    Thanks,

    Jellenie

  • Thank Jellenie for your quick response.

    i will try the experiment to set configuration registers before enabling error registers.

    below is the register map settings configured for ADC:

    -------------------------------------------------------------------------------
    Register ADDR DATA (16/24-bit) 8-bit CRC.
    -------------------------------------------------------------------------------
    ERROR_EN : 0x07 00 08 04 (REF_DET_ERR_EN & SPI_CRC_ERR_EN)

    CONFIG_0 : 0x19 09 64 1E (Bipolar, REF_BUFP, AIN_BUFP, AIN_BUFM, Gain = 16)
    CONFIG_1 : 0x1A 09 62 B1 (Bipolar, REF_BUFP, AIN_BUFP, AIN_BUFM, Gain = 4)
    CONFIG_2 : 0x1B 09 60 D4 (Bipolar, REF_BUFP, AIN_BUFP, AIN_BUFM, Gain = 1)
    CONFIG_3 : 0x1C 09 40 22 (Bipolar, REF_BUFP, AIN_BUFP, , Gain = 1)
    FILTER_0 : 0x21 01 00 10 C3 (sync, single cycle, FS=16
    FILTER_1 : 0x22 01 00 10 F9
    FILTER_2 : 0x23 01 00 10 EF
    FILTER_3 : 0x24 01 00 10 8D
    CHANNEL_0 : 0x09 A1 0B 06 (CONFIG_2, FILTER_2) AIN8-11
    ADC_CTRL : 0x01 04 C4 6D

    Thank you.

    Regards,

    Kalyan

  • 0
    •  Analog Employees 
    on Oct 19, 2020 6:57 AM 1 month ago in reply to KALYAN

    Hi,

    It seems that you are using internal reference in two of your configuration settings, but the internal reference is disabled at ADC_Control. Can you confirm this please?

    Thanks,

    Jellenie

  • Hi Jellenie,

    No all the configuration settings uses REFIN1(+)/REFIN1(−). last byte is the 8-bit CRC byte. below is the configuration details:

    CONFIG_0 : 0x19 09 64 (0x19 is address)
    CONFIG_1 : 0x1A 09 62 (0x1A is address)
    CONFIG_2 : 0x1B 09 60 (0x1B is address)
    CONFIG_3 : 0x1C 09 40 (0x1C is address)

    Thanks,

    Kalyan

  • 0
    •  Analog Employees 
    on Oct 21, 2020 5:26 AM 1 month ago in reply to KALYAN

    Hi Kalyan,

    Apologies. I misinterpret the data. I've noticed that you are in single conversion mode. Is this correct? 

    In single conversion mode, the AD7124-8 performs a single conversion and is placed in standby mode after the conversion is complete.

    In standby mode, most blocks are powered down. Diagnostics can be enabled or disabled while in standby mode. However, any diagnostics that require the master clock (reference detect, undervoltage/overvoltage detection, LDO trip tests, memory map CRC, and MCLK counter) must be enabled when the ADC is in continuous conversion mode or idle mode; these diagnostics do not function if enabled in standby mode. To exit standby mode, the AD7124-8 requires 130 MCLK cycles to power up and settle.

    Can you confirm if the error register was read upon exiting standby mode?  

    Thanks,

    Jellenie