We are doing a data acquisition system based on the AD7768-1 and I’m seeing some strange behavior of the DOUT (MISO) line, that ultimately results an incorrect data acquisition.
In some cases the DOUT line resets too early, leaving a really small capturing window for the MCU/FPGA to latch the data. Attached are some scope shots to illustrate the problem. We are seeing this issue on register accesses and data acquisition mode too. The SCLK frequencies varies from a couple of 10KHz up to 20MHz.
From multiple tests it seems this happens only with the last HIGH bit of a transfer, indifferent where the bit is located in the overall transfer.
Do you know anything about this behavior? Maybe we are missing something? Do we need to use an external pull-up for the SDO line?
Thank you for your help!