ADC Recommendation : 8/16 channel ADC with PGA (without mux), 16+ bits resolution with synch / simultaneus sample/read feature

Hi,

Looking for 8/16 channel ADC with PGA and Filter (without mux), 16+ bits resolution with synch / simultaneus sample/read feature.

Planning to interface 16x IR sensor outputs to ADC.

Requirements:

Prefer sigma-delta type

Total 16 channels required - May be 2x 8 channel devices with sync feature will also help

Single-ended analog input

minimum 50ksps per channel

16+ effective bits

PGA+Filter+ADC on each channel (without mux) is expected. The channel reads must be simultaneous. It must not use a multiplexer.

Precision simultaneous sampling and reads across all channels is our objective. 1us level of synchronization is expected across all channels.

Could you please advice suitable part suggestion for this application requirement. Thanks in advance.

Parents
  • 0
    •  Analog Employees 
    on Aug 24, 2020 2:17 PM 6 months ago

    Hi SriDevi, 

    Have a look at AD7771. You'd use 2x and SYNC them together. Options for lower speed/input current are AD7770 and AD7779.

    https://www.analog.com/en/products/ad7771.html

    Will depend on the range of output from the IR transducer as to the right fit - see what you need.

  • Hi MClifford,

    Yes our part investigation also narrowed to AD7771 part only. Thank you for the inputs.

    "DIGITAL RESET AND SYNCHRONIZATION PINS" section in the AD7771 datasheet details about connecting the SYNC_OUT/SYNC_IN pins toe stablish the synchronization of sampling the inputs between the multiple devices. But there is no detailing provided regarding multiple devcies for synchronization on the SPI interface side.

    It is not clear on how the digital data read via SPI could be synchronized between the 2 devices. Shall we have the 2 ADCs on the same SPI bus for control/data interface with the FPGA/SoC - using individual chip selects? Else do we need separate SPI buses for each ADC? Please advice on how the multiple device data synchronization could be done. If any application note or document exists please provide the same for our reference.

    Hope via SYNC_OUT/SYNC_IN simultaneous sampling synchronization is achieved between 2 devices across all the 16 channels. Let me know if my understanding is correct.

    Thanks.

  • 0
    •  Analog Employees 
    on Aug 25, 2020 10:26 AM 6 months ago in reply to SriDevi

    Hi SriDevi,

    Note you have two different interfaces: DOUT and SPI, to clock out data. Using DOUT, the AD7771 is the master and controls the serial clock.

    If using SPI, you would need at least a dedicated CS per AD7771. The other SPI lines could be shared. If sharing lines, note that it may impact the maximum throughput achievable as you need to clock 32 bits multiplied by the number of channels. What is the intended output data rate? 

    Are the two AD7771 next to each other? If so, a shared MCLK and reseting the digital filter simultaneously would do for getting the two devices synchronized. For more details on synchronizing AD7771s I'd refer to the below article.

    https://www.analog.com/en/analog-dialogue/articles/sigma-delta-adc-architecture-averts-disrupted-data-flow-when-synchr-critical-distributed-systems.html

    Regards,

    Lluis.

  • 0
    •  Analog Employees 
    on Aug 25, 2020 10:29 AM 6 months ago in reply to SriDevi

    Hi SriDevi, 

    Firstly, yes - you can achieve synchronization with common MCLK and SYNC pulse applied to both devices. This is a requirement to have the conversion synchronized from the ADCs. Getting the data out then, there are options:

    For the data path from the converter there are a couple of options depending on which digital host you are using. What is the digital host/processor that you intend to connect to? with 50ksps and 16 channels of data you have to be careful on getting all the data out and the required serial clock speed.

    Options:

    a) Output data over the SPI interface for interface to  uC.

    In this case you would use same SCLK and combination of the DOUT from the different CS to control the communication lines. 

    here it takes longer to get the data back and you are unable to actively read back from internal registers from the control register set.

    b) output data over the DOUT where the ADCs are master and DCLK clocks out the data

    Here you can get the data from all 16 devices faster if you wish to have more data lines. It also allows the device to be controlled actively over SPI interface separately.

    It will typically be used connected to FPGA and is more of a SPORT connection as opposed to an SPI interface.

    Boils down to:

    1. what your digital host is?

    2. is it important to receive the results from each of the 16 devices to give more time for processing for each sampling instant on a point to point basis?

    With this info we can advise further.

  • Sorry for the late revert. Just resumed the project activity. The digital host is Zynq 7020 SoC.

    Have provisioned for 2 ADCs in the PCB for the 16 single ended unipolar analog inputs. With respect to the data output, SPI will be the data interface to the FPGA SoC and we have provided individual SPI bus to each ADC.

    1. Would like to understand if the simultaneous synchronous sampling of all the analog inputs be done by using START, SYNC_IN/OUT signals as depicted in Fig.110 of the AD7771 datasheet?

    So as per this configuration, the MCLK will be supplied to both the ADCs and the START pulse be provided to the first ADC, which will output SYNC_OUT in synchronous to the MCLK which will be fed to the SYNC_IN of both the ADCs to reset the digital filters of both the ADCs simultaneously.

    2. In the PCB to accomplish this multiple ADC architecture as per Fig.110, need input on the suggested method of MCLK routing

    (a) can the MCLK be daisy-chained i.e., routed to ADC1 first and then to ADC2?

    or

    (b) do we need to bi-furcate the MCLK trace at the source point & keep the MCLK traces to each ADC the same length to avoid skew? 

    Thanks.

Reply
  • Sorry for the late revert. Just resumed the project activity. The digital host is Zynq 7020 SoC.

    Have provisioned for 2 ADCs in the PCB for the 16 single ended unipolar analog inputs. With respect to the data output, SPI will be the data interface to the FPGA SoC and we have provided individual SPI bus to each ADC.

    1. Would like to understand if the simultaneous synchronous sampling of all the analog inputs be done by using START, SYNC_IN/OUT signals as depicted in Fig.110 of the AD7771 datasheet?

    So as per this configuration, the MCLK will be supplied to both the ADCs and the START pulse be provided to the first ADC, which will output SYNC_OUT in synchronous to the MCLK which will be fed to the SYNC_IN of both the ADCs to reset the digital filters of both the ADCs simultaneously.

    2. In the PCB to accomplish this multiple ADC architecture as per Fig.110, need input on the suggested method of MCLK routing

    (a) can the MCLK be daisy-chained i.e., routed to ADC1 first and then to ADC2?

    or

    (b) do we need to bi-furcate the MCLK trace at the source point & keep the MCLK traces to each ADC the same length to avoid skew? 

    Thanks.

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