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LTC2320-16 SDR/DDR pin control


I have a question regarding the SRD#/DDR pin (pin 23) of the LTC2320-16:
According to the datasheet, this pin should be tied to GND or OVDD. Is it also possible to control this pin from an FPGA?
When driving the pin from an FPGA, the SDR#/DDR pin will change its level after the LTC2320-16 has powered up. Is this ok?

Looking forward to your answers,