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AD7767 2's complement output not as described in Data sheet


I am using the AD7767 24 bit ADC. It is measuring a strain gauge load cell. The front end has a programmable gain differential amplifier Renesas ISL28635. The Reference voltage is 3.3 volts.

What I am experiencing is a decrease in signal range from the ADC. When I vary the strain gauge from an unloaded condition, the output is near zero with an offset. As I increase the load the ADC values increase until I reach +Vin of 2.475 and a -Vin of 0.825 The ADC output is 7FFFFF. When I increase the load to get a +Vin of 3.3v and -Vin of 0 volts the ADC output is FFFFFF. Also when I reverse the load where +Vin is 0 volts and -Vin is 3.3 volts I get 000000.

The data sheet shows the input range to get 7FFFFF is +Vin 3.3 volts and -Vin 0 volts. Why is there a discrepancy in the output?

Any thoughts would be appreciated.

  • This is a question which was not picked up at the time of posting. My apologies for this. I know that in replying now the relevant time has passed for this information. I am updating the response so that others may find it useful.

    From the description it seems as though you may be missing the MSB in your read back. AD7767 MSB is loaded prior to the first SCLK. It is not an effective interface implementation on the device. If you look at all your raw code read outs you'll be able to tell if this is occuring by examining the final two bits. If they are always the same - i.e.00 or 11 then you have missed the MSB in read back.

    ON your particular examples:

    In your readings at fullscale you are getting all 1's. As you rightly say this ought to be:

    0111 1111 1111 1111 1111 1111 to represent positive full scale.

    If you miss the MSB you will get the LSB repeated 

     111 1111 1111 1111 1111 1111 1  where this final 1 is the repeated LSB.

    Similarly for negative FS the device returns this code in 2's comp:

    1000 0000 0000 0000 0000 0000 

    However if the MSB is missed again the LSB would be repeated.

    To solve

    - read back on the SCLK rising edge. SCLK falling edge clocks out the data on serial output

    - if using CS  ensure polarity of the first edge after DRDY and CS falling edge is a rising one -this will allow the MSB to be read as the MSB is already on the DOUT when CS falls. if not you can miss the MSB as the falling edge will clock MSB-1.

    IF you are not using CS - gate the SCLK prior to the DRDY rising/falling and ensure that the first edge of the SCLK after DRDY pulse is the rising edge which you use to acquire the MSB.

  • Thanks your reply was helpful in finding the problem. It turns out the problem with the setup of the SPI port

    hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;     // caused the readout to miss the MSB 

    The change below resolved it

    hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH; 

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