I'm having trouble communication with the AD7795 via SPI. I'm using the chip in single conversion mode.
The AD7795 is connected to an FPGA via the SPI interface.
The FPGA first issues a reset command by clocking out 32 1's into the DIN port of the ADC to make sure that the SPI interface is in sync. Then it issues the following words in this order:
1. 0x10 (to indicate that the next write is to the configuration register)
2. 0x1010 Selects channel zero for reading
3. 0x08 (to indicate that the next write is to the configuration register)
4. 0x204A Selects single read mode and enables the CLK output from the ADC
5. wait for DOUT to go high
I've attached a screenshot of the interface behaviour for the sequence above. For some reason the DOUT signal never goes high, and the CLK signal doesn't show up on the output pin.
Any ideas what could be the issue here? Is the CS signal behaviour correct? Is the gap between words sufficient?