Digital interface to the AD7825

I have some questions

  concerning the digital interface to the AD7825.

 

  1. It appears from your spec that the rising edge of RD causes the rising edge of EOC.  True?

  2.   The falling edge of EOC indicates the conversion is complete and the data is ready to be read.  True?

  3.    The width of EOC is spec'd as a min and max (t4).   Since the width of EOC seems to be dependant  on when the data is read, why is there spec on the width of EOC.

 

 

  thank you in advance,

Parents
  • 1> The rising edge of RD can cause the rising edge of EOC but the rising edge of EOC will occur after EOC has been logic low for 110ns max. There is no figure in the datasheet to illustrate this but in page 12 under "Mode 2 Operation", it explains that a read can be done outside the low pulse of the EOC.

    2> Yes, the falling edge of EOC indicates that conversion is complete and data can be read.

    3> The width of EOC low is not dependent on the data being read. If a read is performed within the EOC low pulse and the RD line goes high before the 110ns is up for the EOC low pulse then the EOC line will also go high

Reply
  • 1> The rising edge of RD can cause the rising edge of EOC but the rising edge of EOC will occur after EOC has been logic low for 110ns max. There is no figure in the datasheet to illustrate this but in page 12 under "Mode 2 Operation", it explains that a read can be done outside the low pulse of the EOC.

    2> Yes, the falling edge of EOC indicates that conversion is complete and data can be read.

    3> The width of EOC low is not dependent on the data being read. If a read is performed within the EOC low pulse and the RD line goes high before the 110ns is up for the EOC low pulse then the EOC line will also go high

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