AD7683 and Sampling clock

Hi,

I need to know how to vary the sampling frequency of AD7683?

It is written that the sampling clock is internal.

I need to use this for 1KHz and 256Hz sampling,is this possible?

  • 0
    •  Analog Employees 
    on Jun 17, 2011 12:25 AM over 9 years ago

    So sampling bursts of 2.9 MHzs at 1KHz something.  This sums it up pretty succinctly.  So you'll want to set up a timer to trigger a conversion every 1ms (1kHz sample rate).  The conversion is performed by performing an SPI read (at least 22 clocks, typically one would provide 24 clocks).  The speed of the SPI clock (DCLOCK) can be any rate you choose, up to 2.9MHz.

  • Thanks Tim.

    I think I got it finally

    Few other things I found:

    1.AD7683 can not be interfaced with ADSPBF537 as we have only 16 bit SPI register and we can not store 24 bit result into this register.It is also not possible to give 24 bit clock. CS/ can be some external port pin and can be low for any amount of time.But this is not possible for SPI SCK and SPI data.As soon as the SPI is initiated it will start loading the data it can be FF as the line can be high or any data on SPI.It is always the first 16 bits will be loaded into SPI RBDR with Clock.

    I don't know how the datasheet says compatible with BF53x.Even the Eval board uses some other unknown DSP kit.

    Is there any other way to make it compatible with the BlackFin ? SPI is not TM  which means it is not standard Motorola SPI.

    2.The Settling time requirement highlighted asks to check for 0.0015% for capacitive array load.The Capacitance in pF is not mentioned.

       I am using AD623 it gives settling time graphs.I am not sure it gives for 0.0015% of Vstep or not?

       In my application I think I need not worry about the Settling Time as it is just 1KHz sampling .Pls confirm this !!

    3.AD7685 is a fantastic option as it has 0.6 LSB INL  at the same cost and a higher sampling also. It has 25MHz SPI it suits with my SD card clock.

    4.AD7885 Serial output waveform Shows it is 16 bit SPI.It means it is compatible with BalckFin and SPI (TM).It does not need SPI clock to be active during conversion.Pls confirm this as I need a ADC to be compatible with BlackFin BF537 and I am planning for rigorous DMAs.

    Pls give your expert opinions !

  • 0
    •  Analog Employees 
    on Jun 20, 2011 11:46 PM over 9 years ago

    See my response below for your queries.

     

    1. Although the eval board uses the Altera's Flex 6000 series, the AD7683/85 are compatible with the SPI, QSPI, digital hosts, and BlackfinRegistered ADSP-BF53x or ADSP-219x. The SPI protocol became a standard de facto that was developed by Motorola, but It does not have an officially released specification or agreed by any international committee.

     

    2. You don't need to worry about the settling time for this application.

    3. As I recommended earlier, the AD7685 is a better fit for your application.

    4. See (1). Usually, our ADC can use either 3-wire or 4-wire SPI interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections, useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications.  When conversion is completed, the AD7685 enters the acquisition phase and powers down. In other words, When CNV goes low, the MSB is output onto SDO and the remaining data bits are then clocked by subsequent SCK falling edges. So, the SPI clock does not need to be active during the conversion.

     

    Hope this makes sense.


    BTW, We have couple of CFTLs done on the AD7685 that may be helpful. Here are the links:

    http://www.analog.com/en/circuits-from-the-lab/CN0130/vc.html

    http://www.analog.com/en/circuits-from-the-lab/CN0104/vc.html

    Regards,
    Maithil

  • Hello Maithil,

    Yes this makes lot of sense.I will not use AD7683 for sure thanks for AD7685 suggestion and explanations.

    My team is trying to read AD7683 and BF537 EZ kit over SPI.It looks like it is not possible to read this on BF537.

    When we connected a FPGA and with which we can generate any type of serial interface,so we generated timings similar to what is mentioned in Datasheet,we got the results.

    Blackfin will never be able to generate such timings over SPI.

    This is the precise reason because of which you might be using Altera eval board.

    Data sheet probably means Glued compatiblity with BF53x.

    Has anyone performed a SPI read of AD7683 over BF53x?16 bit SPI register and 24 bit clock requirement for 16 bit data?

    What we can do here is put CS/ low and read it three times in 8 bit SPI mode and keep doing this continuously as we need to supply the clock.

    I don't know whether this will work?

    Before I do similar exercise over AD7885,I just need to ask you a very simple question:

    1.Can we interface AD7885 gluelessly to BF53x?

    2

    CNV, which initiates the conversions, to be independent of the readback timing (SDI).

    What is the meaning of that?

    Do I have to do a Low high and Low of the CNV?

    In SPI most of the Time the CS/ or CNV will be high so what will the device will do,keep continuing the conversion??And of what data?old acquired data again?

    When we use DMA reads,I don't think we can play with CS/ and toggle it between every read.

    Pls tell me suitable method to do a simple typical BlackFin SPI read of the device.

    .

  • 0
    •  Analog Employees 
    on Jul 27, 2011 12:29 AM over 9 years ago

    Hello Chaitanya,

    Sorry for the delayed response as I was out on a vacation.

    I am not sure why you can't read AD7683 data over SPI using the BF537 EZ kit.

    To answer your other questions,

    1. You should be able to interface the AD7685 with the BF53x.

    2. The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high and the chain mode is selected if SDI is low.

     

    As shown in the figure below, SDI is high and it could be useful to bring CNV low to select other SPI devices, such as analog multiplexers, but CNV must be returned high before the minimum conversion time (0.5us) and held high until the maximum conversion time (2.2us) to avoid the generation of the BUSY signal indicator. When CNV goes low, the MSB is output onto SDO, which is synchronized to SCLK. The remaining data bits are then clocked by subsequent SCK falling edges.When conversion is completed, the AD7685 enters the acquisition phase and powers down.

    Which mode are you planning to use? with or without busy indicator?

    I'll defer you to Blackfin processor folks for an advise on suitable method to do a simple typical Blackfin SPI read of the device.

    Regards,
    Maithil