AD7683 and Sampling clock

Hi,

I need to know how to vary the sampling frequency of AD7683?

It is written that the sampling clock is internal.

I need to use this for 1KHz and 256Hz sampling,is this possible?

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  • 0
    •  Analog Employees 
    on Jun 16, 2011 12:30 AM

    This particular device uses the SPI clock (DCLOCK) as the clock for the conversion.  You can run the DCLOCK up to 2.9MHz.  The sample rate is determined by the /CS signal than by the DCLOCK signal, as you can run the DCLOCK at the higher speed (2.9MHz) for any sample rate you choose.  Using 1kHz sample rate as an example, and a 2.9MHz DCLOCK, the transaction will take ~8.3us (24 clocks @ 2.9MHz).  The rest of the time (out of the 1ms period) will be available for the SPI to be used for other devices.  Given that this is a sucessive approximation ADC, the input is sampled at the falling edge of /CS and held for the entire conversion, thus jitter on the DCLOCK has little effect on the conversion.  I believe the internal clock mentioned in the data sheet to be an error.  I'll try to verify.

    Regards,

    Tim

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  • 0
    •  Analog Employees 
    on Jun 16, 2011 12:30 AM

    This particular device uses the SPI clock (DCLOCK) as the clock for the conversion.  You can run the DCLOCK up to 2.9MHz.  The sample rate is determined by the /CS signal than by the DCLOCK signal, as you can run the DCLOCK at the higher speed (2.9MHz) for any sample rate you choose.  Using 1kHz sample rate as an example, and a 2.9MHz DCLOCK, the transaction will take ~8.3us (24 clocks @ 2.9MHz).  The rest of the time (out of the 1ms period) will be available for the SPI to be used for other devices.  Given that this is a sucessive approximation ADC, the input is sampled at the falling edge of /CS and held for the entire conversion, thus jitter on the DCLOCK has little effect on the conversion.  I believe the internal clock mentioned in the data sheet to be an error.  I'll try to verify.

    Regards,

    Tim

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