AD7683 and Sampling clock

Hi,

I need to know how to vary the sampling frequency of AD7683?

It is written that the sampling clock is internal.

I need to use this for 1KHz and 256Hz sampling,is this possible?

Parents
  • 0
    •  Analog Employees 
    on Jun 13, 2011 11:05 PM

    Hi Chaitanya,

    The AD7683 has a Serial Data Clock Input - DCLOCK. You can vary the sampling frequency by changing the speed of a clock to DCLCOK input Since the conversion result on DOUT pin is synchronized to DCLOCK.

     

    Note that the AD7683 is compatible with SPI, QSPI, digital hosts, MICROWIRE, and DSPs. The connection diagram is shown in Figure 25 and the corresponding timing is given in Figure 2 of the datasheet.

    A falling edge on CS\ initiates a conversion and the data transfer. After the fifth DCLOCK falling edge, DOUT is enabled and forced low. The data bits are then clocked, MSB first, by subsequent DCLOCK falling edges. The data is valid on both DCLOCK edges.

    The AD7683 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in Figure

    24 in the datasheet, so this makes the AD7983 ideal for low sampling rates such as 1KHz and 256Hz (even of a few Hz).

    Hope this helps.

    Regards,

    Maithil

Reply
  • 0
    •  Analog Employees 
    on Jun 13, 2011 11:05 PM

    Hi Chaitanya,

    The AD7683 has a Serial Data Clock Input - DCLOCK. You can vary the sampling frequency by changing the speed of a clock to DCLCOK input Since the conversion result on DOUT pin is synchronized to DCLOCK.

     

    Note that the AD7683 is compatible with SPI, QSPI, digital hosts, MICROWIRE, and DSPs. The connection diagram is shown in Figure 25 and the corresponding timing is given in Figure 2 of the datasheet.

    A falling edge on CS\ initiates a conversion and the data transfer. After the fifth DCLOCK falling edge, DOUT is enabled and forced low. The data bits are then clocked, MSB first, by subsequent DCLOCK falling edges. The data is valid on both DCLOCK edges.

    The AD7683 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in Figure

    24 in the datasheet, so this makes the AD7983 ideal for low sampling rates such as 1KHz and 256Hz (even of a few Hz).

    Hope this helps.

    Regards,

    Maithil

Children
No Data