AD7683 and Sampling clock


I need to know how to vary the sampling frequency of AD7683?

It is written that the sampling clock is internal.

I need to use this for 1KHz and 256Hz sampling,is this possible?

  • 0
    •  Analog Employees 
    on Jun 13, 2011 11:05 PM

    Hi Chaitanya,

    The AD7683 has a Serial Data Clock Input - DCLOCK. You can vary the sampling frequency by changing the speed of a clock to DCLCOK input Since the conversion result on DOUT pin is synchronized to DCLOCK.


    Note that the AD7683 is compatible with SPIRegistered, QSPITm, digital hosts, MICROWIRETm, and DSPs. The connection diagram is shown in Figure 25 and the corresponding timing is given in Figure 2 of the datasheet.

    A falling edge on CS\ initiates a conversion and the data transfer. After the fifth DCLOCK falling edge, DOUT is enabled and forced low. The data bits are then clocked, MSB first, by subsequent DCLOCK falling edges. The data is valid on both DCLOCK edges.

    The AD7683 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in Figure

    24 in the datasheet, so this makes the AD7983 ideal for low sampling rates such as 1KHz and 256Hz (even of a few Hz).

    Hope this helps.



  • Hi,

    What it means is that I can not sample the ADC continuously !

    What I understood from you is DCLOCK is the one which decides the sampling.

    Is this correct?I mean DCLOCK can go in MHz (1.2MHz) how it will work then?

    Usually it is some down conversion of DCLOCK can sample this.

    This is good for Single Shot mode.

    I have few questions

    1.It means that Micro Controller's SPI will be continuously busy by giving the clock at desired sampling rate.

    2.We can not put anything else on that SPI as the clock will be too slow

    3.Aperture Jitter will be there as the sampling clock is derived from DCLOCK.

    4.What is the use of internal clock mentioned at the start of the Datasheet.

    5.Is there any EOC ?to interrupt the DSP?

    Pls keep this thread alive !

    Usually the SPI clock is just for reading the Sampled data.It can be of any value and periodically DSP will read it by giving a high clock data quickly so that it can use the SPI bus for other ADCs or devices.Sampling is done by an internal or external clock with or without PLLs,results are just made ready in the SPI buffer to read.

    Pls comment in the point of contiuous reading of the ADC ,probably with a seperate crystal.

  • 0
    •  Analog Employees 
    on Jun 16, 2011 12:30 AM

    This particular device uses the SPI clock (DCLOCK) as the clock for the conversion.  You can run the DCLOCK up to 2.9MHz.  The sample rate is determined by the /CS signal than by the DCLOCK signal, as you can run the DCLOCK at the higher speed (2.9MHz) for any sample rate you choose.  Using 1kHz sample rate as an example, and a 2.9MHz DCLOCK, the transaction will take ~8.3us (24 clocks @ 2.9MHz).  The rest of the time (out of the 1ms period) will be available for the SPI to be used for other devices.  Given that this is a sucessive approximation ADC, the input is sampled at the falling edge of /CS and held for the entire conversion, thus jitter on the DCLOCK has little effect on the conversion.  I believe the internal clock mentioned in the data sheet to be an error.  I'll try to verify.



  • 0
    •  Analog Employees 
    on Jun 16, 2011 1:12 AM

    I think Tim has already addressed some your concerns.

    First off, I'd recommend you to use the AD7685 for your application, which is a higher speed -250KSPS part with more functionality at the same price. It has two modes - CS mode and chain mode. It also has a BUSY signal indicator to interrupt the digital host and trigger the data reading.

    Keep in mind that a minimum of 22-clock cycles are required for AD7683 16-bit conversion and DOUT goes low on the DCLOCK falling edge following the LSB reading.

    Let me clarify that you can control the sample rate with CS and then serial clock has an effect of that in terms of conversion time.

    As I said before DCLOCK is an input of the AD7683, so you will have to provide an external clock. I wouldn't worry about the jitter here as this is a low-speed application. The internal clock mentioned in the datasheet is not an error. Usually there are two types of clocks in our SAR ADCs -one internally generated for the conversion and one applied externally to read back the data -both of them run asynchronously. The AD7683 doesn't have the capability to generate interrupt or BUSY signal.

    What's your end application?



  • Hi,

    I am bit confused.

    My application is automotive diagnostic,telematics and measurement,ECU related etc.4 Bridge Sensors then MUX(4:1 x2) and instru AMP and a ADC.

    I need to detect vibration,shock,sudden accleration and tri axial accleration.

    I am in selection process.As you know automotive application is cost sensitive especially in India.

    Presently I am using BF537.

    See if I assumed TIM's explanation that the ADC conversion process is CS/ dependant.You make 1KHz timer and in its interrupt just do a SPI read of the device which will automatically make the CS/ low and SPI clock will be in MHz may be as he suggest 2.9MHz so I willl get the result in SPI data register of the processor.

    This brings me back to the same question how the device knows the samplig clock ? as 2.9MHz is just a communication clock or is it that the device will sample in the intervals of 1KHz but sampling clock of 2.9MHz.So sampling bursts of 2.9 MHzs at 1KHz something like that.

    As per Maithil 22 times the serial clock is the sampling clock,

    2.9MHz / 22 does not make 100Ksps. I think it will be 2.2 MHz clock to get 100 Ksps and for 1Ksps 1K*22 = 22KHz so again pretty slow SPI clock needed.

    This again makes me think that this particular device is may be for Single Shot mode only.Was this device targeted to particular OEM and not for a general market?

    I request both of you to express your thoughts, I am bit slow on things.