I use the AD7918 to measure internal voltages of my electronic, namely 15V, 5V and 3.3V itself. Due to the Power Supply topology, the 15VDC are generated ny a separate switch mode regulator than the 5VDC and 3.3V (derived of 5V). Thus I cannot exclude conditions with the 15VDC being applied to the input channel of the ADC w/o having the 3.3V already powering the ADC itself. For the ADC failed with a significant rate in the last two weeks I took a deeper look into the Datasheet and by this I found (somewhere in the text)...
"If CS, DIN, or SCLK are applied before AVDD, there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to AVDD. "
Does this indicates potential problems with signal being applied to the analog input channel w/o AVDD (3.3VDC) being applied (which may happen in my circuit)? Curiously we built more than thousand units up to now w/o facing any issue and last weeks 4 ADC failed with defect measurement of the 15VDC, that initiated my search for a root cause. Can the analog input be protected by higher ohmic voltage divider scaling to minimize any input current into the analog channel?
Thanks a lot,Carlhermann
How are you dividing down the 15v input to the ADC? I presume you have some sort of resistor divider there. If an overvoltage occurs (as during powerup), the ESD structures will turn on and conduct current from the 15v source. You need to limit this current to <10mA in order to prevent damage to the analog inputs (see page 18 of the data sheet, Analog Input section).