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AD7687 Operates Single-Ended, not differential.

I have a board with three AD7687's that are acting like single-ended ADC, not differential.

The parts are marked C03 #535.
The devices operating in Chain Mode With Busy Indicator, connected as shown in the datasheet.
Sample rate is 5K samples/second.
SCK period is 110ns (9MHz) 50% duty cycle.

VDD and VREF are both 5.0 Volts. VIO is 3.3V.

I have verified all signals with an oscilloscope and all clocking looks valid, and the data being read by the software matches what I see on SDO with the scope.

All three devices are acting similarly. The following data was collected from one device, and is repeatable.

With a differental input:
IN+ at 1.8V, IN- at 3.25V (a differential of -1.45 V) I get an output around 15XX Hex.
IN+ at 3.7V, IN- of 1.7V (Differential of +2.0V), Output is around 55XX Hex.
Varying between these two conditions, I get ONE intermediate step around 2BXX hex.

If instead, I operate single ended:

IN+ 1.8V, IN- GND, Output is 5BXX.
IN+ 3.6V, IN- Ground, Output is B7XX.
These outputs are about what I would expect from a single-ended ADC.
Also, when I vary between these two conditions, I get nice uniform steps as would be expected.

Going one step further, Grounding IN+ and applying any positive value to IN-, the output is 0000.

Anybody have any clues? Or are my parts not really AD7687's?

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  • Hello Arnie,

    I looked at your schematic, which seems OK. I am little concerned about the plot though. Did you mean the SDO of U8 in the bottom trace? U8 is the first device to clock out the data, and then subsequenlty U7 and U6.

    Note that In the chain mode with easy inidcator, When all ADCs in the chain have completed their conversions, the near-end ADC (U8 in your schematic) SDO is driven high. This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host.  Each ADC in the chain outputs its data MSB first, and 16 × N + 1 clocks are required to readback the N ADCs.

    If this problem persists in your application, you can send over couple of parts to us and we'll have a look at them.

    Regards,
    Maithil

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  • Hello Arnie,

    I looked at your schematic, which seems OK. I am little concerned about the plot though. Did you mean the SDO of U8 in the bottom trace? U8 is the first device to clock out the data, and then subsequenlty U7 and U6.

    Note that In the chain mode with easy inidcator, When all ADCs in the chain have completed their conversions, the near-end ADC (U8 in your schematic) SDO is driven high. This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host.  Each ADC in the chain outputs its data MSB first, and 16 × N + 1 clocks are required to readback the N ADCs.

    If this problem persists in your application, you can send over couple of parts to us and we'll have a look at them.

    Regards,
    Maithil

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