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AD7687 Operates Single-Ended, not differential.

I have a board with three AD7687's that are acting like single-ended ADC, not differential.

The parts are marked C03 #535.
The devices operating in Chain Mode With Busy Indicator, connected as shown in the datasheet.
Sample rate is 5K samples/second.
SCK period is 110ns (9MHz) 50% duty cycle.

VDD and VREF are both 5.0 Volts. VIO is 3.3V.

I have verified all signals with an oscilloscope and all clocking looks valid, and the data being read by the software matches what I see on SDO with the scope.

All three devices are acting similarly. The following data was collected from one device, and is repeatable.

With a differental input:
IN+ at 1.8V, IN- at 3.25V (a differential of -1.45 V) I get an output around 15XX Hex.
IN+ at 3.7V, IN- of 1.7V (Differential of +2.0V), Output is around 55XX Hex.
Varying between these two conditions, I get ONE intermediate step around 2BXX hex.

If instead, I operate single ended:

IN+ 1.8V, IN- GND, Output is 5BXX.
IN+ 3.6V, IN- Ground, Output is B7XX.
These outputs are about what I would expect from a single-ended ADC.
Also, when I vary between these two conditions, I get nice uniform steps as would be expected.

Going one step further, Grounding IN+ and applying any positive value to IN-, the output is 0000.

Anybody have any clues? Or are my parts not really AD7687's?

  • Hello,

    It would be helpful if you can share your schematic and scope screenshots showing input and output signals (SDO, SCK, CNV, etc.).

    Are you using one of the driver amplifiers recommended in table 10 of the datasheet?

    Note that the AD7687 is a true differential 16-bit part and it does not have a single-ended or pseudo-diff mode, so when you try to use the part in this mode it is still 'looking' at the world in a differential way and therefore it can NOT be driven in a single-ended or pseudo-diff mode. The AD7687 samples the voltage difference between the IN+ and IN− pins. The AD7687 requires the inputs to be completely anti-phase of each other between 0 V and REF with their DC common-mode around VREF/2. It may not work at all if you ground either the IN+ or IN- pin.

    Regards,

    Maithil

  • maithil wrote:

    Hello,

    It would be helpful if you can share your schematic and scope screenshots showing input and output signals (SDO, SCK, CNV, etc.).

    Are you using one of the driver amplifiers recommended in table 10 of the datasheet?

    I don't have a good way to capture from the scope I am currently using, and do not have a sharable schematic.

    The AD7687's are being driven by a pair of MAX7420 Switched capacitor filters, but I have also been testing by directly driving the AD7687 from a programmable function generator ( using due caution to keep the input within safe operating limits of the device).

    Note that the AD7687 is a true differential 16-bit part and it does not have a single-ended or pseudo-diff mode, so when you try to use the part in this mode it is still 'looking' at the world in a differential way and therefore it can NOT be driven in a single-ended or pseudo-diff mode. The AD7687 samples the voltage difference between the IN+ and IN− pins. The AD7687 requires the inputs to be completely anti-phase of each other between 0 V and REF with their DC common-mode around VREF/2.

    I am trying to use it in true differential mode. The connecting of IN- and IN+ to ground have been experiments to try to understand the parts after seeing the strange operation in differential mode.

    It may not work at all if you ground either the IN+ or IN- pin.


    The trouble is, with IN- grounded seems to be the only way the part wants to work.

    Right now I have connected a programmable function generator directly to the IN+ and IN- inputs.

    1Hz sine wave, 3Vp-p.

    With it connected differentially, with 2.5V common-mode (VREF=5V), I get three steps in my data: 15B5H, 2B99H, 55B7H.

    If I connect it with IN- grounded, and the signal on IN+, centered at 2.5V with a +/- 1.5V swing (3Vp-p), I get a beautiful sine wave on my data display, with the data values centered around 8000H. It is behaving exactly as I would expect a AD7685 Psuedo device to operate, including the output being straight binary (not two's complement) centered at 8000H.

    The parts are marked C03 #535, which to my reading of the data sheet indicate they are indeed AD7687's. Is there any possibility that there was a batch of mismarked parts? These were purchased about 16 months ago, but not used until now.

    Thanks for any possible help,

    Arnie

  • Hello Arnie,

    It seems weird that it works in psedo-differential mode, but not in differential mode.

    It's hard to figure out the solution to your problem without actually looking at your scope screenshots and schematic.

    The parts are indeed AD7687 as per thier markings. I don't think they are missmarked parts.

    You need to ensure that the AD7687 inputs IN+ and IN- are completely anti-phase (180 degree out of phase) of each other between 0 V and VREF.

    The AD7687 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with sufficient decoupling 10uF (X5R, 0805 size) ceramic chip capacitor between the REF and GND pins for the optimum performance.

    An optional reference buffer such as AD8031 is recommended as shown in figure 34.

    Have you followed the layout guidelines from the datasheet?

    The input impedance of the AD7687 is not very high (like few MΩ for traditional opamps). We recommend that its inputs be driven using a low impedance source driver amplifier as shown in table 10.  The RC filter is also recommended as shown in figure 27. The key is the analog front (OpAmps, etc.) must settle within the acquisition time (1.8uS min) of the ADC.

    BTW, What's your end application and estimated annual volume?

    Regards,
    Maithil

  • I may have found the problem.

    We're using the parts in the QFN-10 package, which has the exposed pad on the bottom. The manual says this pad MUST be grounded. OOPS! We didn't. We'll be doing some microsurgery on the board to try and remedy that so I can continue testing.

    I've seen some strange things in circuits with missing grounds over the years, and this fits right in with them, so I'm betting on this fixing the issue. I'll reply back with the results.

    Arnie

  • OK, that wasn't it, no change in behavior from before.

    All clocks are generated by a LPC2378 microcontroller.
    CNV is a 3.3V 4KHz Square Wave.
    SCK is a 3.3V 500KHz Square Wave.
    SCF_CLK is a 100KHz Square wave for the switched-capacitor filters (MAX7420's).

    Normally, three differential accelerometer modules are connected to the inputs on J3.

    I have tested by connecting a programmable function generator to these inputs so that I have complete control over the test conditions to ensure that the signals are differential around a 2.5V center.

    I have also eliminated the MAX7420 filters by connecting the function generator directly to the IN+ and IN- inputs of the 7687's.

    All of these test conditions have generated similar results.

    Attached are a schematic and scope capture.

    The capture shows:
    CNV (top trace)
    SCK (middle trace)
    SDO from U6 (bottom trace)

    In this trace, IN+ and IN- are both at 2.5V (differential input of 0V).

  • Hello Arnie,

    I looked at your schematic, which seems OK. I am little concerned about the plot though. Did you mean the SDO of U8 in the bottom trace? U8 is the first device to clock out the data, and then subsequenlty U7 and U6.

    Note that In the chain mode with easy inidcator, When all ADCs in the chain have completed their conversions, the near-end ADC (U8 in your schematic) SDO is driven high. This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host.  Each ADC in the chain outputs its data MSB first, and 16 × N + 1 clocks are required to readback the N ADCs.

    If this problem persists in your application, you can send over couple of parts to us and we'll have a look at them.

    Regards,
    Maithil

  • maithil wrote:

    Hello Arnie,

    I looked at your schematic, which seems OK. I am little concerned about the plot though. Did you mean the SDO of U8 in the bottom trace? U8 is the first device to clock out the data, and then subsequenlty U7 and U6.

    Note that In the chain mode with easy inidcator, When all ADCs in the chain have completed their conversions, the near-end ADC (U8 in your schematic) SDO is driven high. This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host.  Each ADC in the chain outputs its data MSB first, and 16 × N + 1 clocks are required to readback the N ADCs.

    If this problem persists in your application, you can send over couple of parts to us and we'll have a look at them.

    Regards,
    Maithil

    We are using SDO of U8 as the BUSY indicator before reading any data.

    The trace is of U6. This would be the same as the trace of SDO-A in figure 46 in the data sheet. This same data is eventually clocked through to SDO of U8, which is where we are actually reading it. I used the trace of U6 because it was easy to isolate the output of just one converter, and verify that I was indeed clocking 16 bits of data from it.

    I have one of your eval boards on order, expected middle of next week. We'll see what that tells me.

    Thanks,

    Arnie

  • With the EVAL board, does "stand-alone"  mode mean that with power connected to the board, the on-board DSP will exercise the ADC? Or do I have to provide the control signals for the ADC myself?

    Are there any other connections (resets, etc.) that need to be connected? The documentation for "stand-alone" is extremely sparse.

    Thanks,

    Arnie

  • Yes, you can use the AD7687 eval board in stand alone mode, where the on-board DSP will exercise the ADC. However, you need to provide the external control signals on the eval board such as CNV, SCK, SDI, etc. and power supplies such as +3.3V,  +/-5V, +12V, VIO, etc.

    Regards,

    Maithil

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