A few questions about the clock input on this device.
1) is it OK to clock at a slower speed than 48 MHz? I only need to sample at about 200k SPS instead of 3M SPS and was having problems with glitches at higher clock speeds. Are there parameters within the device that necessitate making the conversion within a certain amount of time? I didn't see anything in the data-sheet but wanted to check.
2) instead, i looked at purchasing the AD7476 (1M SPS) or AD7466 (200k SPS). Both of those are far more expensive on Digi-key, are they inherently better devices? I would have assumed the faster devices are better..
3) In the datasheet (for AD7276) where the serial interface is described (p22 right column) it mentions that in applications with slower clock speeds it is possible to read data on the each rising edge of SCLK.. it seems like in these cases instead of the MSB coming on the 3rd rising edge it arrives on the second rising edge.. This would create a problem if I can't be sure where the MSB is!! At what frequencies does this occur?? When can I be sure that the MSB will arrive on the 2nd rising edge? When can I be sure that the MSB will arrive on the 3rd rising edge? I am using a positive edge triggered flip-flop to synchronize the CS with SCLK.