Clocking on AD7276

A few questions about the clock input on this device.

1) is it OK to clock at a slower speed than 48 MHz?  I only need to sample at about 200k SPS instead of 3M SPS and was having problems with glitches at higher clock speeds.  Are there parameters within the device that necessitate making the conversion within a certain amount of time?  I didn't see anything in the data-sheet but wanted to check.

2) instead, i looked at purchasing the AD7476 (1M SPS) or AD7466 (200k SPS).  Both of those are far more expensive on Digi-key, are they inherently better devices?  I would have assumed the faster devices are better..

3) In the datasheet (for AD7276) where the serial interface is described (p22 right column) it mentions that in applications with slower clock speeds it is possible to read data on the each rising edge of SCLK.. it seems like in these cases instead of the MSB coming on the 3rd rising edge it arrives on the second rising edge.. This would create a problem if I can't be sure where the MSB is!!  At what frequencies does this occur?? When can I be sure that the MSB will arrive on the 2nd rising edge?  When can I be sure that the MSB will arrive on the 3rd rising edge?  I am using a positive edge triggered flip-flop to synchronize the CS with SCLK.


  • 0
    •  Analog Employees 
    on Jan 30, 2012 8:23 PM


    I moved this question about the AD7276 to the Precision ADCs community.  Please continue the discussion here.



    EngineerZone Community Manager

  • 0
    •  Analog Employees 
    on Feb 1, 2012 12:16 PM

    Hi winman,

    1) Yes it is fine to clock at a lower speeds than 48MHz. The minimum is specified in Table 5 at 500kHz SCLK rate, therefore your 200k SPS rate will be fine. 

    2) The AD7276 A grade is a lower performance version than AD7276 B grade and therefore cheaper.

    The AD7276 A grade is also lower performance than the AD7476, AD7466  in terms of dc specs (offset and gain) and ac specs (SNR and SINAD).

    3) When using a full speed 48MHz SCLK with the AD7276, data must be read into the processor on the falling edge of SCLK. So in this case, on the 2nd falling edge the MSB is driven out from the AD7276 and it is read into the processor on the 3rd falling edge. The reason for this is the access time (t4) on the interface is 15ns max, so it will take 15ns for the data to be guaranteed on the bus from the edge that it was driven our of the part on (guaranteed across temperature and power supply voltage). With a 48MHz SCLK, the SCLK period is 20.8ns, so we know the data won't be available on the bus for the rising edge following the falling edge when it was driven out, you will need to wait for the subsequent falling edge.

    However, with a slower clock, say 10MHz, the clock period is now 100ns. With this SCLK rate you know the data will be available to be clocked into the processor on the rising edge following the falling edge that it was driven out on. Does this make sense?  Take note, you need to ensure that you allow for enough setup time (which is specified by your processor) to ensure this will be fine in your setup. You will not have any issue using a SCLK as slow as 500kHz.