1) Regarding the AD1974, the data sheet mentions that 16 channels are supported. However, the example of daisy chaining the AD1974 only shows two addition devices - is it in fact possible to connect 4 x AD1974 together?
2) If 4 devices are supported, how are they connected, are there any example schematics etc?
3) Can a single 12.288mhz oscillator drive all the clocks directly and support 48khz sampling rate for all 12-16 channels?
4) Finally, the data sheet shows the connection with a Sharc with ABCLK going to both TxCLK and RxCLK. Why is does it need to go to TxCLK?
I have attached a diagram that shows the hookup for 4 x AD1974 in Daisy Chain mode. Please note that you must use 24.576 MHz in order to get the clock rates high enough to support 16 channels (BCLK will be 24.576 MHz in this design). In the attached schematic, ADC1 is the BCLK and LRCLK Master and all of the devices are driven from a single 24.576 MHz source. The only reason that the ABCLK would be routed to the TxCLK would be to have all of the ports in the SHARC synchronous; there is nothing about the AD1974 that would require this.
Thanks again for the detailed response.
We are looking to interface these devices with the SPORT interface on the Blackfin. So can I just double check with you the interface between ADC1 and the Blackfin:
ASDATA1 of ADC1 -> DR0PRI (SPORT0 Primary Rx Data)
ABCLK of ADC1 -> RSCLK0 (SPORT0 Rx Clock)
ALRCLK of ADC1 -> RFS0 (SPORT0 Rx Frame Sync)
Is there any need to connect ABCLK to TXCLK0 on the Blackfin?
Sorry to be annoying, but do you think you could re-post a higher res image of the daisy chain. I think I understand most of the connections - but just to double check it would be good to read the net labels.
I will send a hi res version of the hookup to you offline.
I have asked a BlackFin expert to chime in regarding your SPORT questions.
This began as a question about the SHARC, and the most recent response appears to have switched over to Blackfin for the processor. I'll try to address them both. In the old SHARC processors (at least the 2106x and 2116x families), the SPORT in multi-channel mode had to have the transmit clock pin as an input, and the transmit clock had to be externally connected to the receive clock to synchronize the internal circuitry, so the circuit you referenced is accurate for those processors. In the more recent SHARC processors (e.g., 2146x), the design implementation changed to half-SPORT modules, so the transmit and receive circuitry is completely decoupled. thereby removing this requirement.
For the Blackfin processors, the multi-channel mode of operation forces an internal connection between TSCLK and RSCLK, so the only clock pin that needs to be connected externally is the RSCLK pin (and it can be either an input or an output).
Thanks for the replies.
Joe, I brought up the Sharc processor initially as the AD1974 only shows example connections to it, and not the Blackfin. The Blackfin is the target processor for our app.