AD7995 reading problem

Hi-

I moved this question about the AD7995 to the Precision ADCs community.  Please continue the discussion here.

Thanks,

AndyR

EngineerZone Community Manager

Hi Joe

could you send me the whole write frame/config byte you are sending?

and the whole frame/data bytes you are getting back?

screenshots from the scope of the SDA and SCL lines would be helpful. Does your scope have an I2C interpreter?

what values do you see with channel 0 at 5V, 0V and have you tried reading any of the other channels?

Jimmy,

I'm afraid I can't do much right now; they're doing some construction work back in our lab and I can't get in there.

I do have a simulation waveform I can share that shows my FPGA setting the configuration register to 0x10; this transfer looks exactly the same in the lab. (I have a generic I2C slave model in place of the ADC in my simulation.) In the screen capture, the transfer occurs between the yellow cursors; the ADC I2C slave signals are at the bottom of the window, and the I2C master signals are above them.

I can also get a waveform that shows an I2C read from that slave model. While it isn't a read from the actual chip, it would at least show how the transfer occurs under the control of my FPGA. If that would be helpful, let me know and I'll set up a simulation to generate that.

Due to the design of our board, we can't directly control the voltage levels on channel 0. The device driving the input to channel 0 has several sources for that signal that we can choose from, but the levels it puts out are controlled by conditions within that device that we have no control over. I have measured the voltage levels on the channel 0 input for each of the possible sources, and they are at reasonable values and are different for each source.

If I could get into the lab, I could set the ADC up to disable channel 0 and enable one of the other channels, and then read that back. I think I tried that at some point already, and got the same results as with channel 0, but I can't swear to that.

Joe

Hi Joe

on your FPGA sim is the timescale that same as in the real application?

from the screenshot the I2C clock apprears to be running at 3.5MHz.

Have you scoped the SCL line on the physical board to verify it is running at 400kHz?

Jimmy

Jimmy,

Yes, I sped up the clock in the simulation so that I could see the transfer take place without waiting an hour. On the board it is definitely running at 400kHz.

Joe

Hi Joe.

have you been able to get back to the lab yet?

also if  I could see the section of the circuit the ADC is in that might be helpful along with the scope traces from the actual board.

Jimmy

Jimmy,

We can finally get back into the lab; unfortunately, the project's been cancelled, so I have to stop work on this now. Thanks anyway.

Joe