I confronted with encoder emulation failure,
My board dos not correctly work with AD2S1205, but work with AD2S1200 :-) The same board!!!
The encoder emulation with AD2S1205 is not comparable with AD2S1200.
The reset time at rdc is the same. (300ms) The crystal is the same (8.192MHz) The position vailue (from parallel port) show alwais correct in all cases (with AD2S1205 and AD2S1200) When Resolver is plugin, i have no LOT and DOS failure.
The difference, what i see:
When Resolver is disconnected of AD2S1205, then clock the A and B signals of Encoder with 1,024MHz and correct offset.
By AD2S1200, the same A and B signals of Encoder are clocking with 256kHz. The LOT and DOS failure are active in both cases.
When resolver is stopping, i see by AD2S1200 encoder outputs the last active value (0 or 1),
but the AD2S1205 encoder outputs (A and B) generates futhermore a kind of pwm signal sequence with correct offset. (see picture: signal A)
By AD2S1200 emulation generate the encoder 1024 impulses per rotation, but the follower ic generate a kind of pwm signal sequence. (very much more than 1024 impulses)
I'm already tested two ic AD2S1205, with the same result. :-(
Operate the encoder emulation by AD2S1205 of the same kind as by AD2S1200? Are the encoder output driver the same?
The AD2S1200 and the AD2S1205 should produce very similar encoder outputs.
As regards compatibility between the two devices the AD2S1205 input range is wider than the AD2S1200 and covers the range of the AD2S1200 so that should not be an issue. The phase lock range is tighter on the AD2S1205 and should not be exceeded while exceeding the range on the AD2S1200 while not recommended would not have as big an impact. The AD2S1205 does not require a RESET after a LOS to prevent a false null condition.
One item to note is that the AD2S1205 requires resistors between the Sin & SinLo and Cos & CosLo inputs to detect a complete resolver disconnect.
Is the output you are seeing with both a disconnected and connected resolver?
The CLKIN range for the AD2S1205 is 8.192MHz +/-25% so a 4.096MHz clock would be outside of spec.