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EVAL-AD7634 - External serial clock

Hello,

I recently acquired an EVAL-AD7634 board and wish to operate it as stand-alone (serial slave mode), with a TI DSP TMS320F28335 as serial master. I would like to know if it's possible to provide the serial clock from the DSP to the ADC through the pin SCLK (connector P3 pin C7) . In page 3 of the related datasheet states that in this mode, SCLK (slave serial clock) = MCLK, which is a fixed clock frequency of 40MHz provided by oscillator U12.

Thanks in advance.

Gabriel Brunheira

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  • Hi Alan,

    Thanks again for the help.

    I would like to use the SCLK directly from T4, so I'd need to cut its respective trace. By doing this, is it still possible to get the other buffered signals (for example, SDOUT) from the FPGA? I imagine that cutting the trace from SCLK could compromise the funcionality of the gate arrays for the other signals.

    Ok, now I understand the reason for the 50 ohms, but on the other hand, it seems to be a great waste of power, since this signal is LOW-ACTIVE, which means it will be most of the time on the HIGH state, i.e. dissipating power. Furthermore, the source of this signal cannot be just an ordinary output: it must source too much power.

    Best regards,

    Gabriel

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  • Hi Alan,

    Thanks again for the help.

    I would like to use the SCLK directly from T4, so I'd need to cut its respective trace. By doing this, is it still possible to get the other buffered signals (for example, SDOUT) from the FPGA? I imagine that cutting the trace from SCLK could compromise the funcionality of the gate arrays for the other signals.

    Ok, now I understand the reason for the 50 ohms, but on the other hand, it seems to be a great waste of power, since this signal is LOW-ACTIVE, which means it will be most of the time on the HIGH state, i.e. dissipating power. Furthermore, the source of this signal cannot be just an ordinary output: it must source too much power.

    Best regards,

    Gabriel

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