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EVAL-AD7634 - External serial clock

Hello,

I recently acquired an EVAL-AD7634 board and wish to operate it as stand-alone (serial slave mode), with a TI DSP TMS320F28335 as serial master. I would like to know if it's possible to provide the serial clock from the DSP to the ADC through the pin SCLK (connector P3 pin C7) . In page 3 of the related datasheet states that in this mode, SCLK (slave serial clock) = MCLK, which is a fixed clock frequency of 40MHz provided by oscillator U12.

Thanks in advance.

Gabriel Brunheira

  • Hi Gabriel,

    You can get direct access to the ADC serial interface at the testpoints T3,T4,T5 but you may have to disconnect the traces from the gate array in order to get the desired slave functionality you want. I believe you are correct about the operation of the serial slave mode, this would prevent you driving the SCLK line directly with the DSP because of the onboard oscillator.

    Best Rgds,

    Alan

  • Hi Alan,

    Thanks for the anwser. I didn't quite get it, how i can disconnect these traces from the gate array. Could you please clarify this to me?

    Best regards,

    Gabriel

  • I have one more question: When using the external CNVST (SMB connector J3) , there is a 50 Ohm resistor (two 100Ohm resistors in parallel - R28 and R30) as a pull-down to this input, and a 1MOhm (R36) as a pull-up.

    Is there a reason for this pull-down? Considering that CNVST is a LOW-ACTIVE input, I believe that this impedance would sink too much power (3.3^2/50 = 217mW) while the ADC waits for the Start-Of-Conversion low-pulse.

    When using the internal CNVST, this pull-down doesn't exist (see jumper JP22). Instead, there is only an 49.9Ohm serial resistor (R68).

  • Hi Gabriel,

    You will have to cut the relevant traces to disconnect them from the FPGA or potentially change the FPGA code so they are high impedance and can be driven directly by your DSP. I think the 50 ohms to ground on CNVST is for termination so that the input signal has clean edges. You can remove them if your signal integrity looks good on the PCB.

    Best Rgds,

    Alan

  • Hi Alan,

    Thanks again for the help.

    I would like to use the SCLK directly from T4, so I'd need to cut its respective trace. By doing this, is it still possible to get the other buffered signals (for example, SDOUT) from the FPGA? I imagine that cutting the trace from SCLK could compromise the funcionality of the gate arrays for the other signals.

    Ok, now I understand the reason for the 50 ohms, but on the other hand, it seems to be a great waste of power, since this signal is LOW-ACTIVE, which means it will be most of the time on the HIGH state, i.e. dissipating power. Furthermore, the source of this signal cannot be just an ordinary output: it must source too much power.

    Best regards,

    Gabriel

  • Hi Gabriel,

    If you want the buffered signals from the FPGA then i would suggest not hooking SCLK directly to T4. You could replace the FPGA 40MHz MCLK with your own continuous clock by removing R49 and wiring in at that point.

    Best Rgds,

    Alan

  • Hi Alan,

    At the beginning of my tests with this evaluation board, I tried this idea and it didn't work. Thus I thought I had to use another approach. However, instead of using a continuous clock, I just wired the clock provided by the DSP during the transmission phase of SPI, i.e., a discontinuous clock. The ADC was configured as a serial slave (switches A0: HIGH, A1: HIGH, EXT/INT: HIGH), and although the serial clock from the DSP was reaching the MCLK pin from the FPGA properly, there was no SCLK coming out from it.

    Is there a specific reason to not work in this case?

    With regards,

    Gabriel

  • Hi Gabriel,

    I think if you are using a discontinuous clock like with SPI then i would hook the SPI interface directly to the ADC and disconnect the FPGA. The FPGA MCLK is expecting to see a continuous clock.

    Best Rgds,

    Alan

  • Ok then Alan. Thank you very much for all help! Now I'm able to communicate everything as I expected.

    I would like just suggest Analog Devices to include a direct way to operate this ADC as slave without all these modification in the next rielease of the evaluation board.

    Best Regards,


    Gabriel