I'am using an AD1939 codec and I have a crystal on my board which generates 12,288 MHz (256 x Fs in my case, since I'll use only 48 kHz as a sample rate) and this crystal is connected to the MCLKI/XI pin of the AD1939.
All the systems is connected to a FPGA, which will receive the 12,288 MHz as well.
In my registers, I am going to put the MCLKI/XI for the PLL input in PLL and Clock Control register 0.
Here are my questions :
For the PLL and Clock control register 1, what is exactly the difference between PLL Clock and MCLK for the DAC and ADC source ?
The PLL isn't supposed to generate the MCLK ? In my case, putting both in PLL Clock would be OK ?
About the LRCLK, what is the difference between Slave and Master ? Do I have to provide a 48 kHz signal in master mode or is it self-generated from my MCLK since I provide it with the MCLKI/XI ?
If I have to generate a 48 kHz signal, do you think that generating it from the FPGA would be OK or it would jitter the signal so badly it wouln't be usable ?
About the BCLK, I'm planning to put in Master mode and to put in Internally Generated. If I get it right, it will be generated and I don't have to connect anything on the BCLK ?
They are maybe "silly" questions, and I apologize, I'm new in design creation :-)
Thanks in advance,