Regarding AD7766 interface

Hello,

I have a problem when reading data from AD7766. I have four of ADC in daisy chain. Data is read by Blackfin processor ADSP-BF518 via SPORT configured in multichannel mode. I'm using the AD7766 read mode when CS signal is constantly low and SCLK is continuous.

According to the documentation, ADC starts to shift out valid data after falling edge of DRDY impulse. When DRDY signal is high data is invalid regardless of SCLK. The problem is that if SCLK is high comparing to DRDY length (in my case 6,25MHz) and therefore there are few SCLK cycles during DRDY pulse, ADC starts to shift out valid data right after rising edge of DRDY . So, this is a problem itself, but what is much worse is that behavior like this is not constant, I mean the beginning of valid data varies from start to start. Once it's started ok, it is stable. But there is no guarantee that the next time it will start ok too. So, is there any established behavior and what does it depend on? I would appreciate if you gave me an advice on how to deal with that.

Thanks in advance.

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    •  Analog Employees 
    on Aug 2, 2018 4:38 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin
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  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:38 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin
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