I need to interface the ad7450a with the lpc1769 from nxp via SSI. Looking at the time diagrams I suppose It's achievable, but i could be wrong. Could you please take a look a the diagrams and tell me if it's ok?
This is copied from the manual:
"For device configured as a master in this mode, CLK and FS are forced LOW, and the
transmit data line DX is tri-stated whenever the SSP is idle. Once the bottom entry of the
transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to be
transmitted is also transferred from the transmit FIFO to the serial shift register of the
transmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is
shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR
pin by the off-chip serial slave device.
Both the SSP and the off-chip serial slave device then clock each data bit into their serial
shifter on the falling edge of each CLK. The received data is transferred from the serial
shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched."
My only concern is that the clock is forced low after transmission, so i need to make sure the transmit fifo is never empty to maintain the clock active.
Could you please confirm this ?
Thank you very much,