About the signal FRSTDATA on AD7608

Hello everyboby,

I'm going to use AD7608 in a design, and I don't understand the utility of FRSTDATA pin.

I will use serial interface to get my conversions.

I will take BUSY pin on an interrupt of my controller, and once I have an interrupt I will read registers.

Why I should need FRSTDATA pin ?

Many thanks for your help.

Best regards,

Benjamin

  • 0
    •  Analog Employees 
    on Mar 10, 2013 2:41 AM

    Hi Benjamin,

    The FRSTDATA indicates when the first channel V1 is being readback. In serial mode, the FRSTDATA pin HIGH indicates that the result from channel V1 is available on DoutA output data line then returns low after 18th SCLK falling edge. While the Busy pin indicates that the conversion process has started remains HIGH until conversion process of all channels is complete.

    You may choose to use the BUSY pin as the interrupt for the controller. The FRSTDATA allows the data to be read and validate when V1 channel result is available, it would not wait for the results of other channel. This reads the data in advance and would save sometime if this will be use as interrupt.

    Regards,

    Jonathan

  • Hi Jonathan,

    Thanks for your reply.

    I understand, as describe in the datasheet, that the pin FRSTDATA indicated that V1 is actually write on SPI.

    But as it is the host which build the clock, you also know that during the first 18th SCLK you should read channel V1. So I still don't see the utility of FRSTDATA pin.

    Your second argument is more interesting for me !

    If I understand, you mean that the FRSTDATA pin could be used to scan if channel V1 is ready to read when you choose to read result during the next conversion?

    But if you have a SCLK quickest than the conversion time of the other channel there is a problem no?...

    Many thanks for your help.

    Regards,

    Benjamin

  • 0
    •  Analog Employees 
    on Mar 21, 2013 5:44 PM

    Hi Benjamin,

    Apologies for some delay.

    On the AD7608,  You can choose to read the data during conversion, this when BUSY is High.  The falling edge of /CS takes the data output lines out of the three state and clocks out the MSB of the conversion result then the FIRSTDATA goes high indicating that the result for V1 is available on the output data bus.

    Regards,

    Jonathan

  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:48 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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