Post Go back to editing

AD7876 track/hold and conversion time


Hopefully I have posted this in the correct sub-forum.

I am currently investigating an issue with one of our older products that uses the AD7876 ADC. At -40C we see +/- full scale readings, when we expect normal results (analogue range is scaled +/-11V). Checking the timing of the ADC and the input voltage, I observed an anomaly.

The control logic for the ADC, switches the long multiplexer chain, 400ns after the CONVSTART signal goes low, to initialise the conversion.

Will the change of input and resulant noise spike, upset the hold amplifier of the ADC?

The datasheet for the AD7876, states a 2us hold time, our design appears to change the input too soon.

Also, the CS/CONVSTART signal is driven low for 7.8us by the controlling FPGA, the busy signal is ignored. The datasheet states a conversion time of 6.5 to 9us (for internal reference clock). If we are not waiting long enough for the conversion to complete, will this cause results that are either 000h or 3FFh?

Any help appreciated.


  • Hi Ian,

    You mentioned that the anomaly is at -40C, does that mean that the set up is working fine at ambient temperature?

    I am assuming you using the mode 1 serial mode.

    The AD7876  track and hold amplifier acquires signal in less than 2us, noise on the ADC input will certainly affect the acquired sample and result to noisy output for the ADC.

    Please take note that data cannot be read from the part during conversion because the onchip latches are disabled when conversion is in progress. The rising edge of the /CONVST starts the conversion, the /INT pin normally is HIGH and goes LOW at the end of conversion. The data can then be access on the ADC when /INT goes HIGH and /CS and /RD goes low, the /CONVST must be HIGH when this happen.

    What anomaly are seeing on your set up at -40C?



  • Hi Jonathan,

    Yes our system works fine @ ambient and has done for the last 10 years. We have had occasional and now more frequent issues @ -40C.

    The ADC is used in the mode 2 parallel interface. It is controlled by an FPGA. As you know, in this mode the ADC starts the conversion on the falling edge of CS.

    We captured the following waveform with the card @ -40C, it looks like the FPGA is reading too soon.

    We are looking into correcting the timing of the FPGA. The fact that the ADC does not drive the bus, probably indicates why the ADC readings were either 000h or 3FFh +/- a few bits, when we expect values approximately 1E7h and E19h respectively.

    Work is ongoing to check the analogue input waveform, to ensure it is stable at cold.

    The track and hold amplifier, is that operational for the first 2us after CS goes low, thus acquiring the signal?

    In my first waveform plot, you can see the input voltage change dramatically 500ns after the CS signal goes low.

    Thank you for your help so far.


  • Hi Jonathan

    I'm working with Ian on this issue and wanted to add another question.

    We are using the ADC's internal clock, and what we've seen is that conversions take longer at -40C than at ambient. (But still within data sheet tolerances).

    The part can be driven using a TTL compatible clock, what is the highest frquency clock the device can work with?

    The data sheet only refers to 2.5MHz in the Specifications table which produces 8us conversions. Internal clock variability produces 6.5us to 9us conversion times. What frequency would we have to drive CLK to get a conversion time of 7us?

    Many Thanks.


  • Hi Ian,

    It is interesting that it works at ambient. Is the timing the diagram attached, the same when in ambient temperature? I would also suggest, kindly check on the reference volatage at -40C if it still accurate and consistent.

    Hi steve,

    unfortunately the datasheet specified only for 8us conversion time at 2.5Mhz SCLK frequency and on Table 3 of the datasheet, the minimum SCLK cycle is at 370ns, which is probaby about 2.7Mhz max Sclk frequency. I am not yet quite certain on what specific frequency to achieve a 7us conversion time.



  • Hi Jonathan.

    We did get to the root cause of our issue. It was that our circuit does not allow enough time for the maximum conversion time (on internal clock). As I had said, we could see conversion time increasing at cold and unfortunately for some parts (1 in 3) this did mean data was not driven when our circuit was reading it. (as you had said would be the case).

    I am still investigating driving the ADC externally with a 2.7MHz oscillator (a part on order) as that should mean conversion will complete in the time that our circuit allows.

    Another 'solution' we are investigating is to screen devices before fitting, which also leads me to ask.... Analog Devices must perform some form of screening during manufacture. Would this cover conversion time? And is there a procedure where we could order a batch which have maximum conversion of 7.9us? Unfortunately, we are only a low quantity manufacture, so this batch would only be 100 - 150pcs.



  • This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin