AD7091R weirdness

Hi,

I have a AD7091R application which is outputting 'improperly justified data' at lack of a better description. The first bit shifted out doesn't appear to be the MSB, rather the results of a previous conversion - the 8th bit shifted out appears to be the MSB of a new conversion.

Here's a scope shot of the ADC when it's running, with a DC input that's slightly less than half scale. Top trace is /CONVST, second trace is DATA, 3rd trace is SCK and fourth trace is /CS. You can see the "LSB wiggle" happening on the 6th and 7th clocks read out.

I am performing a reset on the ADC, as the datasheet suggests - here's a scope shot of the procedure. I keep the readout clock active but bring /CS high early.

Some other notes on the design:

-VDD is 3.3V, REFIN is tied to the same rail as VDD.

-VDRIVE is a separate 3.3V rail

-Timing is generated with a CPLD clocked at ~40MHz, the SCLK clock rate is 20MHz.

With the CPLD in reset, /CS and /CONVST are high, and SCK is low. When the CPLD is taken out of reset, CPLD reading begins at a ~720KHz sampling rate (~40MHz/55) and /CONVST goes low before anything else happens. During the first read from the ADC, /CS is set high early as shown above in the second capture. Subsequent reads have the /CS line driven normally as shown in the first capture.

I've been through the datasheet many times, trying to find something I've done wrong, but I can't find anything obviously wrong.

Any suggestions? Thanks!

  • I attempted a different reset method; rather than raising /CS early, I reduced the # of SCLK cycles during the first read. Here's a scope shot of the reset procedure:

    Still no success, "LSB wiggle" is still in the middle of the serial data that's read out.

    I'm now out of ideas to try.

  • So I did a bit of experimentation, and I'm fairly certain now that this chip doesn't meet its conversion time spec.

    - I dropped the ADC clock by a factor of 4, and ADC readout worked fine. So I tried /2, and again everything worked fine. Which brings out that whatever's happening here is obviously timing related, even though my read timing falls 100% within the margins in the datasheet.

    - I began to play with the conversion time, and I began to notice something obvious: the "LSB glitch" happens at a fixed time, approximately 1uS, after the beginning of conversion. Here's some shots to back that up:

    (1) Original read timing. Falling edge of /CS happens 680nS after falling edge of /CONV. The cursor (solid yellow vertical line) is placed at 1.04uS - this data bit is always low, and I'm assuming the previous 2 bits have the "LSB wiggle".

    (2) Additional 250nS of convert time added. The "wiggly bits" happen earlier in the readout, but the 1.04uS cursor still falls on the 'always low' bit that follows the "wiggly bits".

    (3) OK, lets go half way between the two intervals used above, and see where the cursor lies. Yup, lands in the same ~1uS time window.

    (5) And finally, lets push this way out. Works perfectly. Unfortunately I can't meet my application's required sampling rate anymore (720KSPS)

    So there you go. I have no idea what goes on in the AD7091R chip internally, but I'm going to make a wild guess that the 1uS time period is how long it takes this chip to perform a conversion, and the messed up data that I'm reading out of it is caused by reading before conversion is complete.

    I have a second board and another AD7091 that I'll build up to see if this is just a problem with a single chip.

  • Hi Gmarsh,

    I would like to ask some questions to have a better understanding of the problem. What is the resolution of the DC input source? It would be much better that the source  is a higher resolution of the ADC. Please also share your schematic if possible. Have you place the decoupling caps recommended on the datasheet?

    Regards,

    Jonathan

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    EZ Admin