AD7895 abnormal timing

Hi,

I know that the users must be based on the timing chart Fig.3 in the data sheet basically. But I think that the care is necessary when an abnormality on the system. In the below 3 cases, what kind of behavior is it? Is there the method to remove it if it becomes abnormal?

1. Input the pulse to SCLK during BUSY:Hi

        The user have found that BUSY keeps Hi level.

2. Input Low to CONVST during inputting SCLK

3. Input 15 or less SCLK pulses

I would greatly appreciate if you could answer for only No.1 by 28/Jul.

And I know the below question to be difficult for you. If you have some advice, please let me know.

Please refer the attached.

Is there the method to remove  keeping Hi of BUSY?

Best Regards,

yk


Timing.ppt
  • 0
    •  Analog Employees 
    on Jul 18, 2013 6:22 AM


    Hi YK,

    Thank you for your question.

    I have seen your graph from your attached file. From the graph start up the system power , it is showing that the VDD has not settled yet and while it is trying to settle in, a digital pulse(CONVST, BUSY and SCLK) were present. On page 3 of the AD7895 datasheet, on the Absolute maximum Rating section. It is showing that the Digital Input voltage levels are dependent on the VDD values ( -0.3V to Vdd + 0.3V). This means that Vdd needs to settle first since the digital levels are dependent on the Vdd values.

    CONVST goes LO puts the track/hold amplifier to its HOLD state and this result the BUSY pin goes HI indicating that a conversion is taking place and go LO when conversion is finish. This will also indicate data is available on the output register. Read operation accesses the data which consist of a 16 SCLK pulses. It is not recommended to put in a SCLK pulses during the falling edge of CONVST which happens to be also the start of the rising edge of the BUSY signal because it will reset the result of the output register.

    Inputting a LO on CONVST during inputting SCLK ( I am assuming during read operation) will result to reset of the shift register meaning it will start to a new conversion cycle.

    The AD7895 counts the serial clock edges to know which data bit from the output register should be placed on the SDATA. 16 SCLK pulses must be provided to access the full conversion result.

    Hope this will help.

    Regards,

    Jonathan

  • Hi Jonathan,

    Thank you for your quick response.

    And I always thank for your careful support.

    I'm sorry, my explanation was short. For the condition of 1 to 3, it is in condition that the power supply is stable.

    1. I know that it is not recommended, but the user want to know the way of escaping when this situation happened without intending.

       As the behavior, the user have found the below.

         - BUSY keeps Hi level and does not go LO.

         - After 16 pulses is input to SCLK, BUSY goes LO.

       Is this behavior reasonable?

       If yes, the user will apply the process of inputting 16 SCLK.

      

    2. I understood that it starts to a new conversion cycle.

    3. When the next CONVST pulse is input, does AD7895 restart?

    And for my last question which is described in slide, I know that it is the behavior during uncertainty period.

    I will recommend to the user that Vdd need to settle first.

    Best Regards,

    yk 

  • 0
    •  Analog Employees 
    on Jul 22, 2013 1:01 AM

    Hi yk,

    Thank you for clarifying.

    The BUSY goes HI when the AD7895 is converting and return LO when conversion is done.

    When BUSY keeps HI and does not go LO,  this looks an abnormal behavior. How long is the BUSY on HI? Was it beyond the specified conversion time? Does this occur always or a specified time or specific settings?

    When this occur please try to reset the shift register by having a falling edge on the CONVST.

    Regards,

    Jonathan

  • Hi Jonathan,

    I apologize for the delayed reply. It has taken time to get the answers from user.

    Answer for your questions
         Q:How long is the BUSY on HI? Was it beyond the specified conversion time? 

         A:The user confirmed it for 200uSec at least. It means that it was beyond the specified conversion time.

         Q:Does this occur always or a specified time or specific settings?

         A:When SCLK is input during Hi of BUSY, this occurs always without specific conditions.

    Reset the shift register

         About your suggestion to reset shift register by having a falling edge on the CONVST, the user tried and the result was not improved. But as a result, BUSY goes LO after the user input 16 SCLK pulses. Please refer the attached file (Timing2). Please let me know how user can reset the device.

    Other question (Please refer the attached file 'Condition of Question')

        1. After the conversion finished and BUSY goes LO, normally 16 SCLK pulses should be input. But if only 15 or less SCLK pulses are input, does next falling edge on the CONVST let AD7895 restart?

        2. After the falling edge on the CONVST, BUSY goes HI. If the extra falling edge on the CONVST during HI of BUSY, does AD7895 restart?

    I'm sorry for asking you many question.

    It would be nice if you could help me.

    Best Regards,

    yk

    attachments.zip
  • 0
    •  Analog Employees 
    on Jul 30, 2013 11:55 PM

    Hi yk,

    No worries about many questions.

    A BUSY HI indicates that the AD7895 is converting and goes LO when conversion is complete and this also indicate that the data is available on the output register. After the conversion, which is about 3.8us after /CONVST falling edge, then a 16 SCLK cyles should be applied to read and clock out the serial data beginning with 4 leading zeros then followed by DB11 - DB0.

    As indicated on the datasheet, a falling edge of the /CONVST will reset the AD7895 and would return to a known state every conversion. Having a /CONVST falling edge between the 16 SCLK cycles or read operation will reset the data register.

    On your second question I need to confirm that,  but since it was not mentioned on the datasheet, I think it is not recommended to have a /CONVST falling edge while converting or BUSY is Hi.

    If would also be helpful if you can share the snapshot of your signal when it is working and when it is having problem. By the way what is the frequency SCLK and the duty cycle of SCLK?

    Regards,

    Jonathan