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AD7763 Filter Download Question

Hi,

 

I am having problems downloading filters to the AD7763. I have tried the example in the datasheet (in Table 16) so that I know the checksum is correct but I am not getting the FILTER_OK or DL_OK bits set in the Status read (the other bits of the Status read are fine - and UFILTER is set).

 

I am convinced that I have no problems with the data timing and I have a good clean clock, frame sync and data. I am clocking at 12.8 MHz.

 

I would be grateful for answers to the following questions:

 

1. Are there are any errors or omissions in the datasheet with respect to the download?

2. Is there any difference between the effects of applying a hardware SYNC (via the SYNC pin) or writing to the SYNC bit in Control Register 1?

3. In Table 16 it is not clear whether the delay for the checksum should be before or after writing the checksum, could you clarify this please?

 

Many thanks,

 

Gary Moore

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  • Hi Gary,

    How wide is your SYNC pulse? Is it synchronous with your MCLK?

    The SYNC is active low, therefore, it is sampled at the falling edge of the MCLK. This should be kept low for a minimum of 4-6 MCLK.

    Also if possible,ensure that all transitions of to be logic high SYNC occur synchronously with the rising edge of MCLK as shown in the diagram below.

    .

    Thanks and Best Regards,

    Chris

Reply
  • Hi Gary,

    How wide is your SYNC pulse? Is it synchronous with your MCLK?

    The SYNC is active low, therefore, it is sampled at the falling edge of the MCLK. This should be kept low for a minimum of 4-6 MCLK.

    Also if possible,ensure that all transitions of to be logic high SYNC occur synchronously with the rising edge of MCLK as shown in the diagram below.

    .

    Thanks and Best Regards,

    Chris

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