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AD7763 Filter Download Question



I am having problems downloading filters to the AD7763. I have tried the example in the datasheet (in Table 16) so that I know the checksum is correct but I am not getting the FILTER_OK or DL_OK bits set in the Status read (the other bits of the Status read are fine - and UFILTER is set).


I am convinced that I have no problems with the data timing and I have a good clean clock, frame sync and data. I am clocking at 12.8 MHz.


I would be grateful for answers to the following questions:


1. Are there are any errors or omissions in the datasheet with respect to the download?

2. Is there any difference between the effects of applying a hardware SYNC (via the SYNC pin) or writing to the SYNC bit in Control Register 1?

3. In Table 16 it is not clear whether the delay for the checksum should be before or after writing the checksum, could you clarify this please?


Many thanks,


Gary Moore

  • Hi Gary,

    I have exactly the same problem as you.

    I want to download a fir to the AD7763. I try to download a complete FIR without success.

    So, I test the example in the datasheet (table 16) and I have the same results than you (filter_ok and dl_ok are not set).

    I have tried more than 20 tests with/without delay between coeff/checksum, etc and it doesn't work.

    nOw, I have no idea to resolve this critical issue.

    Did you find a solution ?

    It would be great if somebody can answer quickly.

    Thanks a lot for any response.


  • Hi Francois,


    Sorry for the delayed reply. Unfortunately I haven’t solved the problem, I got around it by implementing the filter in software – probably not a lot of help to you, sorry.


    I suspect that my problems may have been because my SYNC pulse wasn’t long enough but I’m not sure. I may have another look at it later but it’s a low priority for me now as I have the software work-around and I have other aspects of the system that I need to sort out.


    Very sorry that I can’t be more helpful. If you do find the answer I would be interested to hear.




  • Hi,

    We are looking into this. As of the moment, can you provide details on the settings of your MCLK div?

    On the AD7763 Evaluation board we are set up with an MCLK = 40MHz, CDIV= 0, and SCR = 0. This means that the SCO frequency = 20MHz and the internal clock frequency used is 20MHz.

    With this default we are able to repeatedly download the coefficient example from the datasheet successfully. And we visibly see that the noise floor of our the FFT of our conversions changes as a result.

    Thanks and Best Regards,


  • Hi Chris,

    My configuration is as follows:

    I have 4 AD7763s running together using MCLK = 25.6 MHz and with CDIV = 0 so that ICLK = MCLK/2 = 12.8 MHz.

    We have the decimation set to x16 so our output sample rate is 100 kHz.

    In an earlier version of our design we were running with CDIV = 1 and I’m fairly sure that this worked OK, i.e. we could successfully download the filter. Unfortunately it is not straightforward to re-create that arrangement.

    As I said in my response to Francois, it's possible that my problems are caused by the SYNC pulse width as we discovered that it wasn't as wide as we intended. I have not tried the download since we fixed that but I will let you know if this is successful.



  • Hi Gary,

    After responses from Analog Devices engineers this friday, i succeed to download the 12 defaut coeffcient described in table 16 of datasheet.

    My problem was a bad configuration. I used CDIV = '1' and SCR = '0'.

    Unfortunately, to download the coefficients, it must be CDIV = '0' and SCR = '1' or CDIV = '0' and SCR='0'.

    After that, all status (dl_ok, filiter_ok , ...) was ok.

    I hope this is help you.

    Best Regards


    François NORMAND

  • Hi Gary,

    How wide is your SYNC pulse? Is it synchronous with your MCLK?

    The SYNC is active low, therefore, it is sampled at the falling edge of the MCLK. This should be kept low for a minimum of 4-6 MCLK.

    Also if possible,ensure that all transitions of to be logic high SYNC occur synchronously with the rising edge of MCLK as shown in the diagram below.


    Thanks and Best Regards,


  • Have the same problem with CDIV = '1' and SCR = '1', MCLK = 18,432 MHz, ICLK = 18,432 Mhz.

    Have anybody found any solutions?

    With advance thanks,


  • Hi Chris,

    Sorry for the 3 year delay in my reply! I am looking at this again now as I really need the download to work in our system (I have been using a software filter but now need some extra processing time so need to go back to the filter running in the ADC).

    Our SYNC pulse is 8 x MCLK periods wide and both edges are synchronous with the rising edge of MCLK.

    Just to clarify the system:

    We have 4 AD7763s running together using MCLK = 25.6 MHz and with SCR = 0 and CDIV = 0 so that ICLK = MCLK/2 = 12.8 MHz and SCO = 12.8 MHz.

    We have the decimation set to x16 so our output sample rate is 100 kHz.

    Using the default built-in filter everything works perfectly, we have no problems with synchronisation of the 4 devices. We have also very carefully checked the timing and we are sure that the setup and hold times are met for the register writing and the coefficient writing. We know that the register writes work for all 4 devices because when writing various combinations of the register 1 settings we always get the expected results.

    If we try to write the example filter to the device (all 4 devices at the same time by addressing with the SPI_ALL bit set), the DL_OK or FILTER_OK bits are both 0. However, we have discovered that if we replace the last coefficient by 0xdc9 (this being the correct checksum for the preceding 11 coefficients) the DL_OK bit is then 1. Writing different values for the 13th value (i.e. the one that should be the checksum) have no effect on the status. Writing any value other than 0xdc9 for the 12th coefficient results in the DL_OK bit being 0.

    The implication is that we are failing to write the first coefficient and that it is defaulting to zero. We have not seen the FILTER_OK bit set at all.

    We have very carefully checked the clocking of the register 1 setup word and the coefficients and we are sure that there is not a spurious frame sync prior to writing the first coefficient (which may have explained the extra word of zero).

    We have also tried various delays between writing the register 1 word and the first coefficient and between the coefficients. None of these has had an effect.

    So, do you have any idea what, if anything we are doing wrong? or is there a bug in the device which is relevant to our particular arrangement?

    Also is there an update to the datasheet that may clarify the SYNC timing requirements? The suggestion that the SYNC should be synchronous with the rising edge of MCLK may or may not be compatible with being synchronous with the falling edge of SCO when SCO is equal to MCLK/2.

    Many thanks


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