AD7689 SPI timing chart

Hi, all.

I would like to ask about SPI timing chart for AD7689.

I will use RSC mode and busy indicator.

<Question>

First SCLK seems to capture MSB data in the datasheet,figure 38 and figure 43.

First SCLK should capture busy indicator(My understanding).

Which is correct?

*I think I should refer to AD7693 datasheet,figure 41

Best regards, Jim_Jim

  • 0
    •  Analog Employees 
    on Sep 30, 2013 5:46 AM

    Hi, Jim_Jim.

    For RSC mode with busy indicator, you can refer to both Figure 43 or the RSC portion of Figure 38. The state of CNV at EOC dictates the BUSY indicator - if it is high, BUSY is disabled; if low, BUSY is enabled.  Note that the first 14 SCK rising edges are used to update the CFG register, and the first 16 SCK falling edges clock out the conversion results starting with the MSB.

    Let me know if this helps.

    Regards,

    Karen

  • Hello, Karen

    Thank you for your replying.

    Busy indicator needs 17 SCK falling edge.

    If the first 16 SCK falling edges clock out the conversion results starting with the MSB as you suggested,

    16th SCK falling edge clocks out the LSB?

    (It is written in the datasheet that 16th SCK falling edge clocks out  the LSB+1  )


    If your answer is yes, What the data will be clocked out 17th SCK?

    If no, What the data will be clocked out 16th SCK and 17th SCK?

    Best regards, Jim_Jim

  • 0
    •  Analog Employees 
    on Oct 2, 2013 6:46 PM

    Hi, Jim_Jim.

    It’s entirely upto the user whether they want to use the busy indicator or not for an interrupt purpose. The busy indicator is enabled at the EOC and SDO is returned to low if CNV is low. If host generated only 16 SCK falling edges for SCK in busy enabled mode, you will still get the LSB on the 16th SCK falling edge; however SDO will stay at the same level as LSB. In this mode, the host must assert a minimum of 17 SCK falling edges to return SDO to high impedance because the last bit on SDO remains active. So on the 17th SCK falling edge (Last SCK Falling Edge to SDO High Impedance time delay, tDIS), SDO returns to high impedance (HiZ) as shown in figure 43.

    Note that for SDO to be in a HiZ state, all of the previous data must have been read out.  When CNV is high, SDO is always HiZ.  When CNV is LOW, SDO is HiZ if the previous conversion was fully read, otherwise the last bit read is presented on SDO.  So, if less than 17 clocks given the LSB remains on SDO.  If the LSB of the previous conversion was a logic high, then at EOC you would see the HI-LO transition.  However, if the previous conversion was a logic low, than you would miss that busy indicator.

    Regards,

    Karen