I am designing a digital audio mixer with 16 audio input channels and 16 output channels. A combined DSP/ARM provides processing and Ethernet capabilities.
In order to speed up the process, I'm using a module that includes an OMAPL138. In the module interface I have got available up to 8 McASP channels. Using I2S I could not transmit all the 32 channels. Thus, I would need to use a TDM8 or TDM16 format. TDM 8 will reduce the emissions.
I want to use the AD1939 codec but I would need 4 extra inputs. I was thinking on using a AD1974 to provide those extra inputs but I'm in doubt of what would be the best way of connecting the codecs.
Would it be possible/right to connect two AD1939 in parallel, each of them with their own auxiliary AD1974, like in the diagram? Is the diagram correct, using ASDATA1 and ASDATA2, in I2S mode or is there a better way?
Note: I have not connected the 12.288MHz as it seems that is not really necessary for the McASP ports.
Would it be necessary to use some kind of clock buffering/distribution?
I was not able to see the first attachment you sent. I was able to see the simplified drawing but your description is fine so I don't need the drawing.
Regarding the BCLK polarity I don't think this is a problem. The AD1939 has a lot of flexibility so you can invert the polarity of BCLK or LRCLK in the register settings. It is actually an easy way to swap left and right channels.
Running with only LRCLK will work and I have done it a lot in the lab. Technically, it may be a bit more stable if you supply all the clocks but I have not found this to be a problem. Then when you factor in the simplicity of the design and the reduced number of high speed lines it ends up being a good way to run the parts.
I think it is a good idea to buffer the BCLK output. This part does not have a drive strength register setting. Most of our newer parts have this feature but this one does not.
One thing that does not make sense to me is how the OMAP can function without LRCLK? How does it know where the MSB starts? Then if it somehow finds the proper BCLK cycle and one cycle gets missed due to noise then it cannot recover. I would plan to run LRCLK to the OMAP. I think you will need it.
Everything else in your simplified drawing looks good. You have the correct PLL settings shown. Remember that you will need a different loop filter for the PLL using MCLK vs the PLL using LRCLK. Figure 30 in the datasheet shows this detail.