16 Input / 16 Output Mixer with AD1939 + AD1974

Hi there,

I am designing a digital audio mixer with 16 audio input channels and 16 output channels. A combined DSP/ARM provides processing and Ethernet capabilities.

In order to speed up the process, I'm using a module that includes an OMAPL138. In the module interface I have got available up to 8 McASP channels. Using I2S I could not transmit all the 32 channels. Thus, I would need to use a TDM8 or TDM16 format. TDM 8 will reduce the emissions.   

I want to use the AD1939 codec but I would need 4 extra inputs. I was thinking on using a AD1974 to provide those extra inputs but I'm in doubt of what would be the best way of connecting the codecs.

Would it be possible/right to connect two AD1939 in parallel, each of them with their own auxiliary AD1974, like in the diagram? Is the diagram correct, using ASDATA1 and ASDATA2, in I2S mode or is there a better way?

Note: I have not connected the 12.288MHz as it seems that is not really necessary for the McASP ports.

Would it be necessary to use some kind of clock buffering/distribution?

Parents
  • Hi Dave,

    First of all, thank you very much for your answer,

    I can see how confusing that diagram can be. I left an arrow point pointing somewhere it shouldn't, sorry.

    I include a new diagram where I correct that and have done some changes to clarify it and include your suggestions.

    In the diagram, each AD1974 is slave to their respective AD1939 to the left. In turn, the bottom AD1939 is slave to the top one which is the master to everyone (in light blue), including the processor.

    There are two TDM8 streams, with a fixed sampling frequency of 48kHz. That makes the LRCLK=48kHz, BCLK 12.288MHz and MCLK=12.288MHz.

    [For some reason, I cannot insert images, sorry ->file "CODEC_AD_recommendation"]

    Comments on the diagram:

    MCLK is only needed for the master.

    The rest of the CODECs still need to generate a sampling clock, which they can obtain from scaling the LRCLK in their PLL (filter tuned to the LRCLK frequency).

    The OMAP needs at least BCLK and LRCLK to work. The receiving and transmitting sides are completely independent.

    The processor can derive RxBCLK from TxCLK but, for some reason I don't understand, it is derived as a negated version of the first. I guess that could pose a problem? I prefer to provide a copy of BCLK to both inputs, just in case.

    We have already eliminated one clock buffer and several lines. Let's call this design as A.

    FURTHER IMPROVEMENTS (2nd diagram)

    In order to reduce emissions, minimize the BOM and power and facilitate the routing by eliminating lines, I will try to simplify even further the connections.

    Please find it the corresponding diagram, called "Codec_connection_AD_simplified"

    BCLK:

    It seems BCLK is redundant as can be generated internally with the PLL from LRCLK. So, no need of MCLK or BCLK for either the Slave TDM 1939 or the auxilliary 1974s.

    The OMAP is on a DIMM module, at a maximum distance of 10cm. I don't know the complete capacitance of pins, connector, tracks etc nor the driving capabilities of the AD1939 so, isn't it better to add a buffer and err on the safe side?

    LRCLK:

    LRCLK is sent to the TDM slave and the auxilliary ADCs. PLL filter for LRCLK.

    LRCLK is not sent to the OMAP as it can generate its frame clocks internally when provided with an external BCLK.

    As all the LRCLK connections are point to point connections and not loaded, no need of buffer.

    Are there any drawbacks in this design over the design A? Would you recommend me this simplified design?

    Thank you very much in advance,

    Jordi.

     

    attachments.zip
Reply
  • Hi Dave,

    First of all, thank you very much for your answer,

    I can see how confusing that diagram can be. I left an arrow point pointing somewhere it shouldn't, sorry.

    I include a new diagram where I correct that and have done some changes to clarify it and include your suggestions.

    In the diagram, each AD1974 is slave to their respective AD1939 to the left. In turn, the bottom AD1939 is slave to the top one which is the master to everyone (in light blue), including the processor.

    There are two TDM8 streams, with a fixed sampling frequency of 48kHz. That makes the LRCLK=48kHz, BCLK 12.288MHz and MCLK=12.288MHz.

    [For some reason, I cannot insert images, sorry ->file "CODEC_AD_recommendation"]

    Comments on the diagram:

    MCLK is only needed for the master.

    The rest of the CODECs still need to generate a sampling clock, which they can obtain from scaling the LRCLK in their PLL (filter tuned to the LRCLK frequency).

    The OMAP needs at least BCLK and LRCLK to work. The receiving and transmitting sides are completely independent.

    The processor can derive RxBCLK from TxCLK but, for some reason I don't understand, it is derived as a negated version of the first. I guess that could pose a problem? I prefer to provide a copy of BCLK to both inputs, just in case.

    We have already eliminated one clock buffer and several lines. Let's call this design as A.

    FURTHER IMPROVEMENTS (2nd diagram)

    In order to reduce emissions, minimize the BOM and power and facilitate the routing by eliminating lines, I will try to simplify even further the connections.

    Please find it the corresponding diagram, called "Codec_connection_AD_simplified"

    BCLK:

    It seems BCLK is redundant as can be generated internally with the PLL from LRCLK. So, no need of MCLK or BCLK for either the Slave TDM 1939 or the auxilliary 1974s.

    The OMAP is on a DIMM module, at a maximum distance of 10cm. I don't know the complete capacitance of pins, connector, tracks etc nor the driving capabilities of the AD1939 so, isn't it better to add a buffer and err on the safe side?

    LRCLK:

    LRCLK is sent to the TDM slave and the auxilliary ADCs. PLL filter for LRCLK.

    LRCLK is not sent to the OMAP as it can generate its frame clocks internally when provided with an external BCLK.

    As all the LRCLK connections are point to point connections and not loaded, no need of buffer.

    Are there any drawbacks in this design over the design A? Would you recommend me this simplified design?

    Thank you very much in advance,

    Jordi.

     

    attachments.zip
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