I am designing a digital audio mixer with 16 audio input channels and 16 output channels. A combined DSP/ARM provides processing and Ethernet capabilities.
In order to speed up the process, I'm using a module that includes an OMAPL138. In the module interface I have got available up to 8 McASP channels. Using I2S I could not transmit all the 32 channels. Thus, I would need to use a TDM8 or TDM16 format. TDM 8 will reduce the emissions.
I want to use the AD1939 codec but I would need 4 extra inputs. I was thinking on using a AD1974 to provide those extra inputs but I'm in doubt of what would be the best way of connecting the codecs.
Would it be possible/right to connect two AD1939 in parallel, each of them with their own auxiliary AD1974, like in the diagram? Is the diagram correct, using ASDATA1 and ASDATA2, in I2S mode or is there a better way?
Note: I have not connected the 12.288MHz as it seems that is not really necessary for the McASP ports.
Would it be necessary to use some kind of clock buffering/distribution?
The way you have set up using two AD1939's in parallel to develop two TDM-8 streams looks good. I think that is the best way to do it and the way you are interfacing the AD1974 using the DSDATA2 and DSDATA3 of the AD1939 is correct. I like that you grounded the AUX inputs on the AD1974 and you should also ground the DSDATA4 input of the AD1939. It is always good to not have digital inputs floating around.
Regarding clocking. I am wondering who is the master for the LRCLK and BCLK? My suggestion is to have one of the AD1939 parts be the master. Then it will take the MCLK input and derive the LRCLK and BCLK for the rest of the parts including the OMAPL138. I would strongly recommend to use the PLL on the AD1939. It is good to clock the AD1974 from the AD1939 as you show in the diagram. This will work well.
If the OMAPL138 is to supply the LRCLK and BCLK signals then it will have to generate them based on the MCLK. If this is the case let me know and I will expand on why and how to do this. It is possible but it would have to be done a specific way to avoid clocking issues.
Regarding your question about clock distribution/buffering. This is somewhat dependent on PCB layout but I don't think you will need it for LRCLK or BCLK as long as the lengths are kept reasonably short. MCLK distribution may be required depending on the drive strength of the clock source. You will have to pay attention to signal integrity of these transmission lines. Feel free to contact us when you are working on the PCB layout and before you order the PCBs. We would be glad to review your layout.