AD7625 datasheet questions

, I have the following question(s) about AD7625 Datasheet.

 

  • On page 5, timing specifications, tmsb is stated as 145 nm(max)
  • If you look at page 19 timing diagram from echoed-clock interface mode, tmsb has to elapse before I can burst CLK+ and CLK- from the digital host (FPGA in my case) to latch the data out
  • Should I look at tmsb spec as a time that should not be exceeded?
  • If so, what is the minimum value of tmsb (not stated in the datasheet). I ask this because, for Sample_N, acquisition has to start before the clock burst otherwise I start reading invalid MSB. So if 145ns is the maximum delay, what is the minimum delay? Or in other words what is the relationship between tmsb and rising edge of T_ACQ?

Thank you,

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  • 0
    •  Analog Employees 
    on Nov 28, 2013 4:50 PM

    Hi Frankd,

    The main thing to understand with this interface is that there is a quiet time where the interface cannot be clocked. This is the time where the internal registers could be updating with the new data values. This quiet time is effectively set by the times tMSB and tCLKL.

    Following the conversion start (rising edge on CNV) - you can clock the converter until the tCLKL time has elapsed. The result on the bus will be the result from the previous conversion.

    You can begin to clock the converter again when the tMSB time has elapsed. The time in between is the quiet time.

    The slides illustrate this timing in a way that is easier to understand but both the slides and the datasheet are effectively showing the same thing.

    The user has the choice on where they want to clock the converter as long as they avoid the quiet time.

    Regards,

    ClaireL

Reply
  • 0
    •  Analog Employees 
    on Nov 28, 2013 4:50 PM

    Hi Frankd,

    The main thing to understand with this interface is that there is a quiet time where the interface cannot be clocked. This is the time where the internal registers could be updating with the new data values. This quiet time is effectively set by the times tMSB and tCLKL.

    Following the conversion start (rising edge on CNV) - you can clock the converter until the tCLKL time has elapsed. The result on the bus will be the result from the previous conversion.

    You can begin to clock the converter again when the tMSB time has elapsed. The time in between is the quiet time.

    The slides illustrate this timing in a way that is easier to understand but both the slides and the datasheet are effectively showing the same thing.

    The user has the choice on where they want to clock the converter as long as they avoid the quiet time.

    Regards,

    ClaireL

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