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AD7625 datasheet questions

, I have the following question(s) about AD7625 Datasheet.

 

  • On page 5, timing specifications, tmsb is stated as 145 nm(max)
  • If you look at page 19 timing diagram from echoed-clock interface mode, tmsb has to elapse before I can burst CLK+ and CLK- from the digital host (FPGA in my case) to latch the data out
  • Should I look at tmsb spec as a time that should not be exceeded?
  • If so, what is the minimum value of tmsb (not stated in the datasheet). I ask this because, for Sample_N, acquisition has to start before the clock burst otherwise I start reading invalid MSB. So if 145ns is the maximum delay, what is the minimum delay? Or in other words what is the relationship between tmsb and rising edge of T_ACQ?

Thank you,

  • Hi Frankd,

    We are looking into this and we'll get back to you soon.

    Regards,

    Jonathan

  • Hi Frankd,

    The AD7625 and AD7626 operates the same way, they may differ in throughput rate and some timing numbers. There is certain time clock to achieve maximum throughput, please refer to a  previous post (http://ez.analog.com/message/19768#19768) that may help explain the Tmsb and the clock burst timing.(please refer to the slides on the post).

    You may also want to check the new product AD7961(http://www.analog.com/static/imported-files/data_sheets/AD7961.pdf) which is similar to the AD7625 but with improved AC performance and DC accuracy to name a few.

    Regards,

    Jonathan

  • Hi Frankd,

    The main thing to understand with this interface is that there is a quiet time where the interface cannot be clocked. This is the time where the internal registers could be updating with the new data values. This quiet time is effectively set by the times tMSB and tCLKL.

    Following the conversion start (rising edge on CNV) - you can clock the converter until the tCLKL time has elapsed. The result on the bus will be the result from the previous conversion.

    You can begin to clock the converter again when the tMSB time has elapsed. The time in between is the quiet time.

    The slides illustrate this timing in a way that is easier to understand but both the slides and the datasheet are effectively showing the same thing.

    The user has the choice on where they want to clock the converter as long as they avoid the quiet time.

    Regards,

    ClaireL

  • Thank you Jonathan,

    It seems to me the datasheet is saying one thing and the presentation saying another.

    Page 19 of the AD7625 datasheet, under the heading,"Echoed Clock Interface Mode," 2nd column, last paragraph on that page, 1/2 way down, it states,"Note that tMSB is the maximum time for the MSB of the new conversion result and should be used as the gating device for CLK±"

    In the presentation, Slide 3, it states,"tMSB is the min time from the CNV rising edge until that conversion data is ready to be clocked out – i.e. once tMSB elapses a burst of 16 CLK+/- may be applied for data acquisition

    Also, timing diagram is different as well.  If you look at the timing diagram in the datasheet, page 19 at the bottom of the page, Sample N begins when there is data on D+ and D-.  But in the presentation, slide 3, it shows Sanple N begins when there is no data on these lines.

    So which is correct?  I also looked at the same diagram if the AD7961 and it is the same as the datasheet of the AD7625.

    Thank you and hope you have a Happy Thanksgiving!

  • Thank you Claire and Jonathan for the clarification.   Would you be able to take a look at my new timing diagram just for a sanity check?

    Thank you,

    Frank

  • Hi Frankd,

    Your timing looks good. One clarification on the timing, the acquisition time on the AD7626 is ~50ns when the ADC is running at full throughput (cycle time of 100ns). As the cycle time is extended, all of the extra time adds to the acquisition time so essentially the ADC has more time to acquire the analog input and the driving circuit can be slightly lower bandwidth. So in your case with a 200ns cycle time, the acquisition time will be ~150ns. What throughput do you need in your application?  We also have another similar ADC, the AD7961 which you may be interested in, this is a 5MSPS converter.

    Regards,

    ClaireL

  • We are sampling at 5Msps, which I believe is the fastest rate for this part, hence the 200ns dutycycle.

    Do you think we should move to the AD7961 based on the following?

     

    Since we are on this subject, would there be any effect on performance if we reduced the time from rising edge of CNV to rising edge of first burst clock (currently at 162ns) to 150ns. This would certainly reduce Tmsb below the 145ns (max) spec for the part. I have not directly measured Tmsb rather inferred it from the measurement above. In RTL for the AD7625 driver, we set Tmsb to be a delay of 12 cycles of a 80MHz clock, which is 150ns. Would reducing this delay to 137.5ns (11 clock cycles) violate timing for the part.

  • Hi Frankd,

    Apologies, I was a little confused, I thought you were using the AD7626 which is a 10MSPS version of the AD7625. The AD7961 would be good to consider since it is lower power and higher performance than the AD7625.

    Regarding your timing question, you absolutely need to satisfy the tmsb spec on the AD7625 datasheet, so you need to allow for 145ns from the rising edge of CNV to the first burst clock.

    Regards,

    Claire.

  • Hi Claire,

    In our application we are running the AD7625 at 3 MS/s (tcyc 333 ns).

    we know that we have to wait tmsb (is 145 ns the minimum or maximum spec?) in order to have the D15 bit of sample n (which is the MSB) ready.

    then we can send the 16 CLK pulses in order to start reading the bits of sample n from the ADC. Assuming we are reading at 250 MHz we then need 16/250MHz = 64 ns, right?

    after that delay (tmsb + 16/250MHz) the complete 16 bits word is ready concluding that the total delay is 210 ns.

    is this configuration working in your opinion?

  • Hi Bacciga86,

                       I am assuming you are using the echoed clock mode. . From your setting I think it would work, as referred on fig.29 of the datasheet and as mentioned the only requirement is that the 16 CLK pulses finish before the time Tclkl(110ns) elapses for the next conversion phase or the data is lost. On the Timing Specification Section, the Tcyc-Tmsb+Tclkl  is the time window to read the data.

                      By the way from your setting, there is an idle time of about 123ns prior to the next CNV pulse. May I understand why, because there is still a room to reduce the cycle time and increase the throughput rate.

    Regards,

    Jonathan