AD7625 datasheet questions

, I have the following question(s) about AD7625 Datasheet.

 

  • On page 5, timing specifications, tmsb is stated as 145 nm(max)
  • If you look at page 19 timing diagram from echoed-clock interface mode, tmsb has to elapse before I can burst CLK+ and CLK- from the digital host (FPGA in my case) to latch the data out
  • Should I look at tmsb spec as a time that should not be exceeded?
  • If so, what is the minimum value of tmsb (not stated in the datasheet). I ask this because, for Sample_N, acquisition has to start before the clock burst otherwise I start reading invalid MSB. So if 145ns is the maximum delay, what is the minimum delay? Or in other words what is the relationship between tmsb and rising edge of T_ACQ?

Thank you,

  • 0
    •  Analog Employees 
    on Nov 27, 2013 1:12 AM

    Hi Frankd,

    We are looking into this and we'll get back to you soon.

    Regards,

    Jonathan

  • 0
    •  Analog Employees 
    on Nov 27, 2013 2:07 AM

    Hi Frankd,

    The AD7625 and AD7626 operates the same way, they may differ in throughput rate and some timing numbers. There is certain time clock to achieve maximum throughput, please refer to a  previous post (http://ez.analog.com/message/19768#19768) that may help explain the Tmsb and the clock burst timing.(please refer to the slides on the post).

    You may also want to check the new product AD7961(http://www.analog.com/static/imported-files/data_sheets/AD7961.pdf) which is similar to the AD7625 but with improved AC performance and DC accuracy to name a few.

    Regards,

    Jonathan

  • 0
    •  Analog Employees 
    on Nov 28, 2013 4:50 PM

    Hi Frankd,

    The main thing to understand with this interface is that there is a quiet time where the interface cannot be clocked. This is the time where the internal registers could be updating with the new data values. This quiet time is effectively set by the times tMSB and tCLKL.

    Following the conversion start (rising edge on CNV) - you can clock the converter until the tCLKL time has elapsed. The result on the bus will be the result from the previous conversion.

    You can begin to clock the converter again when the tMSB time has elapsed. The time in between is the quiet time.

    The slides illustrate this timing in a way that is easier to understand but both the slides and the datasheet are effectively showing the same thing.

    The user has the choice on where they want to clock the converter as long as they avoid the quiet time.

    Regards,

    ClaireL

  • Thank you Jonathan,

    It seems to me the datasheet is saying one thing and the presentation saying another.

    Page 19 of the AD7625 datasheet, under the heading,"Echoed Clock Interface Mode," 2nd column, last paragraph on that page, 1/2 way down, it states,"Note that tMSB is the maximum time for the MSB of the new conversion result and should be used as the gating device for CLK±"

    In the presentation, Slide 3, it states,"tMSB is the min time from the CNV rising edge until that conversion data is ready to be clocked out – i.e. once tMSB elapses a burst of 16 CLK+/- may be applied for data acquisition

    Also, timing diagram is different as well.  If you look at the timing diagram in the datasheet, page 19 at the bottom of the page, Sample N begins when there is data on D+ and D-.  But in the presentation, slide 3, it shows Sanple N begins when there is no data on these lines.

    So which is correct?  I also looked at the same diagram if the AD7961 and it is the same as the datasheet of the AD7625.

    Thank you and hope you have a Happy Thanksgiving!

  • Thank you Claire and Jonathan for the clarification.   Would you be able to take a look at my new timing diagram just for a sanity check?

    Thank you,

    Frank