AD7791 conversion latency and Differential input

Hi,

If there is a step change in the analog input, the AD C takes 2 conversion times to generate a valid conversion i.e. the settling time is 2/fadc. If the analog input is continuous and there are no step changes, the AD7791 ADC uses samples gathered for previous conversions to generate the current conversion. In this case, settled conversions are available at fadc.

By default, the AD7791 uses bipolar operation. Coding of offset binary so an analog input of –FS generates a code of 000000 hex, an analog input of 0V generates a code of 800000 hex and an analog input of +FS generates a code of FFFFFF hex. In bipolar mode, the output code is

Code = 2**(N – 1) × [(AIN/VREF) + 1]

For the above, AIN is the applied analog input voltage which is (AIN+ - AIN-). So, for example, if AIN+ = 2V and AIN- = 3V the analog input is -1V.

With the analog input buffer disabled, the absolute voltage on AIN+ and AIN- must be between GND and AVDD. So, AIN+ could be at 0V and AIN- could be at 2.5V which generates an analog input of -2.5V. With the analog input buffers enabled, the buffers require some headroom. So, the absolute voltage on AIN+ and AIN- must be between GND+ 100mV and AVDD – 100mV.

Thanks and best regards,

Chris