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nasty midscale error with AD7684, 16-Bit, PulSAR® ADC

Hi everybody,

I'm evaluating AD7684 ADC with true differential input at

5V supply and an external precision voltage reference of 4.096V.

It is piggy back mounted to an existing board of a running

series, firmware is adapted to its needs. Resolution of the

so far used ADC in the system is around 19bits sampling at 100Hz!

This preface should explain, that it is reasonable to

believe, that external factors should be very limited and

why or how I'm able to comfortably evaluate converted data

externally on a PC using Labview.

What strikes me most is the obvious "midscale error" around

digital code 0x0 when feeding the converter with an triangle

shaped ramp. The jump from 0mV to 2...3mV is equivalent

to about 16 ...24 LSB. This is far too much nonlinearity

for my needs.

Since there is no specification of the midscale error in the

data sheet explicitly, I didn't expect it.

It reads as follows:

INL: ±1 LSB typical, ±3 LSB maximum

Gain Error TMIN to TMAX: typ.±2  max.±15 LSB


Can anyone in the forum explain me what I may have missed during

literature study?

Or does anyone know about this behaviour or the real

performance with this AD7684 converter?

Find attached in pictures both cases, old and new ADC

in respect to noise and midscale transition.

Thanks for reading,

  • Hi Pita,

         The AD7684 is true differential ADC and input to In+ and In- should be 180 degrees out of phase. There are many possibilties that may cause this mid scale error. Have you had some filtering in your circuit? If it is ok, please share your schematic so we can have a better understnading of the problem.  On figure 22 of the datasheet, a typical circuit diagram is recommended for application, and it uses some amplfier to dirve the ADC input.



  • Hi all,

    after another carefull reading of the datsheet I found the answer to my problem myself!

    "Differential positive and negative analog inputs +IN and -IN

    have to be centered at about VREF/2."

    In our earlier case (with a sigma-delta adc) it was at VDD/2, so the board centered inputs

    at 2.5V instead of 2.0V.

    After this little correction, everything ist fine now, we see no steps at midscale anymore!

    Thanks for he opportunity to discuss, even though there was only one participant (me) so far :-).


  • Dear Jonathan,

    as I stated above: problem is solved!

    The driving stages where ok in every respect from the earlier design, expect the DC-offset value of the +IN and -IN had to be adjusted from 2.5V to 2.0V with an exchanged resistor in front of the buffer-OPamp.

    Everything fine, thanks anyway for your contribution.