AD7686 SPI question regarding conversion

I received this question from a customer:

I’ve attached a picture of the logic analyzer capture. I have two questions.

  1. Am I preforming the acquisition/conversion correctly? I have from to read a bunch of analog values. The time to read each analogue value is when the trigger pin goes low. I have about 1.75us to read this pulse. My logic is to hold the conversion pin low so the ADC is constantly sampling. An interrupt catches the falling edge of the trigger pin and I start a conversion (Conversion pin tied to CONV). I hold that pin high for 4.5us. Finally, I bring that pin low and read the values.
  1. The SPI read doesn’t go low between reading bytes. I don’t see that all the time. Is that normal?

I have the SPI clock set at 8MHz. This is the fastest we’ve tried running it. This gives me an acquisition time of 1.71us.

See scope screen shot attached

  • 0
    •  Analog Employees 
    on May 20, 2014 3:24 AM

    Hi Lionel,

         Can we ask for the schematic diagram from the customer to better understand the problem. What mode is the customer using ? Meanwhile I would like to ask the status of the SDI pin. Assuming the customer is using CS 4 wire mode with Busy indicator,  The SDI should be high and a rising edge of the CNV initiates conversion, this forces the SDO pin to high impedance state. SDI pin must return low before the minimum conversion time and remain lo until the maximum conversion time (please refere to fig. 40 p.20 of the datasheet). When conversion is complete, SDO goes from high to lo impedance, this means that data can be clocked out from the SDO pin.

    Regards,

    Jonathan

  • 0
    •  Analog Employees 
    on May 21, 2014 10:37 PM

    Hi Lionel,

        

         From the schematic, I wanted to clarfify on the SDI pin ( SPI_MOSI).  Assuming the customer is using a /CS mode 3 wire without Busy indicator, the SDI pin should be HI or connected to the VIO. Then a rising edge of the CNV indicates start of conversion and when conversion is complete which last a maximum of 1.6us. After this, it will start again acquisition phase. When the CNV goes low it should start clocking out the MSB of the conversion result onto the SDO pin and then subsequent data bits follow on the SCK falling edges.

         Where was the trigger pin mentioned connected? On p.17 of the AD7686 datasheet, figure 34, the acquisition phase start as soon as the AD7686 completes the conversion phase and acquisition ends on the next rising edge of the CNV, this is when it enter the conversion phase again.

    Regards,

    Jonathan

  • 0
    •  Analog Employees 
    on May 22, 2014 12:34 AM

    Jonathan,

    Here is the customer reply:

    We are using the 3 wire setup. Attached are the schematics.

    To simplify question 1, I just want to make sure my logic is sound. Holding the CONV pin low will continuously sample. When I pulse it high, it starts the conversion, and then read from the device.

    I've attached the schematic as well.

    LA

    AD7686.pdf
  • 0
    •  Analog Employees 
    on May 22, 2014 11:57 PM

    Customer reply:

    Yes, the SDI/SPI_MOSI pin is being held high. I think you answered my question. I wasn’t sure when the acquisition phase started. I just wanted to make sure the ADC went back to the acquisition phase after I read the 2 bytes from it. Thank you.