Having trouble operating AD7191 device...

Hello I am Chungmin Han, currently a graduate student in Seoul National University, South Korea.

I am developing a simple pcb using AD7191 to acquire bio-signals and facing several problems so I was hoping I could get

some advice on this. (fascinated how delicate the chip converted with high resolutions, I was informed to use this chip.)

I checked how bio-signals(like ECG) appeared by first acquiring through AD7191 Evaluation Board,

However, I need circuit that transmits data wireless so I used ATmega128 for MCU, bluetooth and

power regulators that we used frequently, but the circuit is not stably working and I can't seem to find out what the problems are.

The descriptions below is value I assigned to the AD7191 chip.


1 - MCLK : We used internal clock source 4.92MHz so Not Connected

2 - MCLK : same as pin1 Not Connected

3 - SCLK : The Pulse for reading ADC result bit is generated from ATmega128 as High-Low sequence 24 times when RDY is down

4 - PDOWN : is tied to GND (Logic 0)

5 - CLKSEL : is tied to DVDD (Logic 1) to use internal Clock 4.92MHz

6, 7 PGA : are tied to output of ATmega128 parallel I/O port with pull-up register (to select either 0, 1)

8 - CHSEL : is tied to output of ATmega128 parallel I/O port with pull-up register (to select either 0, 1)--> we selected AIN3,4 this time

9 - TEMP : is tied to GND (we are not using temperature correction)

10 - NC, tied to GND

11, 12  AIN 1,2

13, 14  AIN 3,4

15, 16  REF +, - : we tied REF+ to half of AVDD and - to GND

17, 18, 19 AGND, DGND : we died altogether

20 AVDD : we tied AVDD to 5V from output of regulator LT1763-5 with 10uF tantal capacitor

21 DVDD : we tied DVDD to 3.3V from output of regulator LT1763-3.3 with 10uF tantal capacitor

22, 24 ODR : are tied to output of ATmega128 parallel I/O port with pull-up register (to select either 0, 1)

23 DOUT/RDY : the output of this pin is connected to one of ATmega128 parallel I/O as input (we are monitoring only one bit)


Power regulator is coupled with appropriate tantal capacitor, and Output logic of ATmega128 is 3.3V(High) and 0V(Low)

The circuit is composed of ATmega128, AD7191, Power regulator(LT1763-3.3, 1763-5), ISP pin, Bluetooth for data transmission, and that's all. (It is also denoted in design & circuit I attached below)

I'm having several problems

:

1. The chip works only when I literally 'touch' the AIN3 pin (I first assumed it was a connection problem and switched the chip or change the wire, but it did not work). When AIN3 touched, with ODR set to be 120, I checked that RDY value went down every 8.33ms(1/120) and pulse generated from ATmega128 that goes into SCLK when RDY ready also clean.

2. The signal we received (while I am touching the AIN3 pin) had major amount of noise, the waveform looked as if it was amplitude modulated, I understand that in 120 Data rate mode, the 60Hz notch is not provided (mentioned in data sheet) thus I checked that power around 60Hz was very dominant. But still after band-pass filtering the signal, the desired ECG did not appear.... The input signal is voltage value.

Is there anything that I am missing to operate AD7191 properly? Any kind of advice or skeptical points would be much of a help.

(So to speak frankly, this is my first time working on hardware design, so I do not have general sense of dealing with chips or circuits, not in real situation though I majored electrical engineering.)

Thank you

Chungmin Han

 






 

  • 0
    •  Analog Employees 
    on Jun 11, 2014 12:38 PM

    Hi Chungmin Han,

    Thank you for coming. Let me handle your query. I'll get back to you with a reply.

    Regards,

    Johnny

  • 0
    •  Analog Employees 
    on Jun 17, 2014 12:36 PM

    Hi Chungmin Han,

    There are few things I'd like to know to help you better. First of all, what is the expected signal of the ECG you are using? For bio-medical signals, a conditioning circuit before the ADC is required. Please take note that the ADC can accept differential input voltage signals +/- Vref/Gain; in your design, this +/- 2.5/Gain.

    Also, if you are using the PGA of AD7191, may I know its configuration?  If I may add, I'd like to know the write and read methods - can you share this also? I recommend to try writing to one of its registers and then read its contents to confirm that the communication to the part is established.

    Regards,

    Johnny

  • The bio-signal I am putting in as input is from PVDF sensors which gives voltage as output, so we directly connect

    the signal output from monocable to the board (this worked on Evaluation board)

    Also, like PGA, CHSEL, CLKSEL, ODA etc, as is circuit design, I apply output of the ATmega High or Low (which in this case 3.3V or 0V) but for simplicity on testing step, I directly applied voltage either 3.3V or 0V from the power source into the AD7191 Pin. Here I attach the signal example screenshot I captured from Evaluation Board software and cable of PVDF sensor. Bio-signal that I am trying to measure is Ballistocardiogram (BCG). Thank you so much again I still haven't clearly fixed yet....

    Sincerly,

    Chungmin Han

  • 0
    •  Analog Employees 
    on Jun 25, 2014 4:47 AM

    Hi ChungminH,

    You mention a 10uF decoupling capacitor on the AVDD and DVDD pins of the AD7191. A 0.1uF ceramic capacitor should also be placed in parallel with the tantalum capacitors.

    Your reference voltage is generated by dividing AVDD by a factor of 2. This is fine. However, the reference inputs of the AD7191 are unbuffered. So, they cannot tolerate large RC values. I recommend that you reduce the size of the resistors from 100K to 10K. Also, I suggest you remove the capacitors on the REF+ and REF- pins. The RC combination that you are using now will cause gain errors. Another option is to remove this attenuation circuit and connect REF+ directly to AVDD. What performance do you need from your system?

    To test the circuit, I suggest you short AIN3 and AIN4 together. Tie the short to Vref. With this configuration, take about 1000 samples. The p-p noise (max conversion minus min conversion) is the p-p noise. It should be typically equal to rms noise x 6.6 (the rms noise is given in the datasheet). If you are getting higher noise from you system, then you need to check the decoupling on the power supplies, check the reference noise.

    I do not understand why pin AIN3 needs to be touched to make the system work. This sounds like a loose connection.

    What is the voltage on the AIN3 pin? Also what is the voltage on the AIN4 pin? The voltage seen by the ADC will be AIN3-AIN4. However, it is important that the absolute voltage on AIN3 and AIN4 is between GND+250mV and AVDD-250mV.

    Can you try the above suggestions? Also, please send me the additional information requested.

    Regards,

    Johnny

  • Hello Johnny,

    Thank you for your detail advice. I corrected the capacitor like you've mentioned.

    I found what was the major problem, I thought SCLK was subordinate to DOUT since if ad data is not ready,

    SCLK would be worthless, but the SCLK had to be held high when ad conversion is undergoing.

    (it was a firmware problem. ATmega AVR code)

    First version of firmware, I assigned SCLK with 24 sequential pulse starting from low state to high, but the chip was very unstable. After I assigned SCLK with 24 sequential pulse starting from state high to low, chip worked very clearly. (The signal below is BCG I acquired with the circuit on breadboard, filtered with MATLAB)

    Like you've mentioned, setting reference as 2.5V is not really necessary, since BCG amplitude is very small, it ranges tenths of mV with gain 64, so applying AVDD to REF+ is fine.

    Thank you so much for your help. My first experience dealing with hardware was pretty much enjoyable. (Sad to think that long time I've struggled was fixed with just one line of c code.....)

    Hope I could also contribute to others with my experience someday. Thank you again.

    Regards,

    Chungmin Han