AD7631: Increase in Noise Floor - Bcoz of Read/Write(Digital Communication)Operation?

Hi,

I am designing an Data acquisition system.

I am using AD7631(18 Bit ADC) in the system.

This ADC's digital lines are interfaced with FPGA through Isolators(ISO7141CC).

The Mode of Operation of ADC during the read operation is "MASTER SERIAL INTERFACE - After convert"

My question is, Whether the data communications which happen in these Digital signal lines affect the performance of ADC.

Let me explain the scenario as follows;

Say, the serial communication clock frequency is 15 MHz. So, the rise time and fall time would be worst case 10% of total period.

But, in this case the worst case scenario occurs when the rise and fall time is less. So, assume 5% of rise and fall time for

calculation.

5% in 1/15Mhz is 3.33 ns. So, during the data transmission the load capacitance(here the input capacitance of Isolator) is charged and discharged between +5V and zero. So, change in Voltage per time (dV/dT - 1.5KV/us ) is high in this case. Since the ADC's digital  ground(ADGND) also connected to Analog ground(AGND) in the board, this high slewing current causes some undesired coupling

which may affects the accuracy (By increasing the Noise Floor) of ADC.

Please confirm that the above observation/assumption is correct or not.

If it is correct, Please suggest the ways to reduce this coupling. I know that by placing a series resistor in the signal line will do the job. But, how to fix the exact value of the resistor.

If anyone can suggest any other methods from your experience to avoid this, it would be really helpful.

Thanks,

Jebas.

Parents
  • 0
    •  Analog Employees 
    on Jul 14, 2014 6:26 PM

    Hi, Jebas.

    It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mbps allowing it to read an ADC result in less than 1 μs. You should not be worried about coupling digital noise into the converter as long as you keep the digital lines away from analog circuitry. It is always good practice to have a series termination resistor that can be adjusted to prevent overshoot on the digital lines. The optimum value of the resistor can be determined by experimentation or simulation if you have that capability.

    Regards,

    Karen

Reply
  • 0
    •  Analog Employees 
    on Jul 14, 2014 6:26 PM

    Hi, Jebas.

    It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mbps allowing it to read an ADC result in less than 1 μs. You should not be worried about coupling digital noise into the converter as long as you keep the digital lines away from analog circuitry. It is always good practice to have a series termination resistor that can be adjusted to prevent overshoot on the digital lines. The optimum value of the resistor can be determined by experimentation or simulation if you have that capability.

    Regards,

    Karen

Children
No Data