AD7960 misbehaves

I am trying to control the AD7960 evaluation board using an FPGA. The output data seems wrong as can be seen in this screenshot (CH1 is CNV+, CH2 is D+, CH3 is DCO+):

The lower bits are noisy, but this is not my main concern at the moment. What is strange is that the 2 bits marked by the cursors (bits 13 and 4, if you count from 17 down to 0) are always 0. Also, applying 0V on the analog input results with a negative digital output. The change in sign is around 0.7V. In the screenshot the input voltage is about 1.5V.

Here is my setup:

The evaluation board is powered with 12V.

All jumpers are at their default position.

Enable bits are EN2=0, EN1=0, EN0=1.

I'm not sure if REFIN is 0v or 2.048V. This is not clear in the evaluation board documentation.

The clock rate is 3MHz. This is to insure low noise. It is also harder to see higher frequencies on the scope.

The signals in the scope seem to have an amplitude of only 300mV. If I disconnect them from the FPGA, the amplitude is 1.8V.

The signals are connected to LVDS pins in the FPGA.

Any hints on what is going on would be welcome.

  • Hello,

    The signals in the scope seem to have an amplitude of only 300mV. If I disconnect them from the FPGA, the amplitude is 1.8V.

    The signals are connected to LVDS pins in the FPGA.

    --> this indicates that the ADC and the FPGA are "fighting" against each other

    (the pins are set to outputs on both components). Are you sure that the LVDS of the FPGA for receiving D- and D+ of the AD7960 are not only set to LVDS, but also as inputs?

    Furthermore LVDS is a differential logic, so you will need to put both differential signals on the oscillospoce.

    If you doubt the output data, you could open JP3 and JP4 on your eval-board and directly wire half your reference voltage on both of the midpins of JP3 and JP4 (= 0V differential voltage).



  • 0
    •  Analog Employees 
    on Aug 21, 2014 6:30 PM

    Hello Udi,

    Seems like it's an issue with your set up. I'm not sure what you mean "V_A- connected to V_B+"?

    You cannot use the ADC board itself in a stand-alone mode without the FPGA board unless you provide all the signals required also for the ADC. The ADC will be in an invalid or unknown state without applying any signal on the EN pins and you will see Vcm = ~ 0.6V.

    If you read the datasheet carefully on page 8 and 17 and look at the ADC schematic closely in its user guide, you need the enable pins (EN3-EN0) to set the operation of the ADC. EN3 = 1 enables the Vcm reference output from the AD7960. The Vcm voltage would be half the value of reference voltage used. For example if you use REF = 5V, you should see Vcm = 2.5V.

    You should not get any error when you connect the ADC board with the FPGA board together and follow the recommended steps from the user guide.



  • I've seen stuck bits on an ADC before (AD7626) if the power up sequence isn't followed. When I turned on all the rails at once, I'd occasionally get stuck bits. If I followed the correct procedure defined in the AD7626, it would work.

    However, on the prototype board I made I forgot to buffer the Vcm pin coming out of the ADC. The driver was turning on before the ADC and loading this pin before the ADC was fully powered. I may not have had an issue if I'd had the buffer.

    All that being said, I think you have a problem with your reference circuit. If REFIN or VCM gets pulled too high or low it can engage the ESD diodes and stick a bit. That was the description of the cause given by my ADI rep.

  • I am applying signals on the enable pins. EN3 to EN1 are 0V and EN0 is 1.8V. I also tried setting EN2 to 1.8V and the rest to 0 for the test signal. This gives a combination of 0s and 1s, but I don't see any documentation on what the test pattern should be.

    Let me give you some background. I'm building a control system that involves ADCs and DACs controled by an FPGA and DSP (using MityDSP-138F). Eventually, we'll make a PCB, but for prototyping I wanted to use the AD7960 evaluation board. I cannot use the SDP board, because it doesn't give me the control I want.

    I connect to the AD7960 evaluation board through the FMC:

    * CNV+, CNV-, CLK+, CLK- are LVDS signals from the FPGA

    * D+, D-, DCO+, DCO- are LVDS signals to the FPGA. I also added 100Ohm resistors for them as shown in figure 2 of the evaluation board user guide.

    * 3.3V is applied to the 3P3V AUX pin.

    * VADJ is also 3.3V.

    * EN[0123]_FMC are connected to 0 or 3.3V as mentioned above. The voltage I measure on resistors R3[1234] is 0 or 1.8V as expected.

    * 12V is applied to the +12V_FMC pin.

    * Grounds from the board and all power supplies are connected together.

  • 0
    •  Analog Employees 
    on Aug 25, 2014 12:44 AM


    About REFIN, I will check our evaluation board to see the default setting of JP7. Have you tried testing with JP7 connected 2 to center?