AD7960 misbehaves

I am trying to control the AD7960 evaluation board using an FPGA. The output data seems wrong as can be seen in this screenshot (CH1 is CNV+, CH2 is D+, CH3 is DCO+):

The lower bits are noisy, but this is not my main concern at the moment. What is strange is that the 2 bits marked by the cursors (bits 13 and 4, if you count from 17 down to 0) are always 0. Also, applying 0V on the analog input results with a negative digital output. The change in sign is around 0.7V. In the screenshot the input voltage is about 1.5V.

Here is my setup:

The evaluation board is powered with 12V.

All jumpers are at their default position.

Enable bits are EN2=0, EN1=0, EN0=1.

I'm not sure if REFIN is 0v or 2.048V. This is not clear in the evaluation board documentation.

The clock rate is 3MHz. This is to insure low noise. It is also harder to see higher frequencies on the scope.

The signals in the scope seem to have an amplitude of only 300mV. If I disconnect them from the FPGA, the amplitude is 1.8V.

The signals are connected to LVDS pins in the FPGA.

Any hints on what is going on would be welcome.

Parents
  • I'm using a Spartan-6 FPGA (model XC6SLX45, through a MityDSP L138F board). The signal pins are defined as LVDS_25. using LVDS_33 gives the same results.

    I tried connecting a different AD7960 evaluation board (the old one got fried). The 5th bit from the left (bit 13) is still always 0. I now realize that the next 3 bits (12, 11, 10) are always 1.

    I seem to have some grounding issue or mis-understanding. I'm using a dual power supply, with V_A- connected to V_B+, to test the ADC. Should AIN+ and AIN- be relative to ground or relative to VCM? The voltage between ground and VCM is 0.6V. I see a VCM_EXTERNAL connection on the board, should I use it?

    I also found a small error in document UG-490. JP7 connects by default B to center and not A to center as is written in table 1.

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  • I'm using a Spartan-6 FPGA (model XC6SLX45, through a MityDSP L138F board). The signal pins are defined as LVDS_25. using LVDS_33 gives the same results.

    I tried connecting a different AD7960 evaluation board (the old one got fried). The 5th bit from the left (bit 13) is still always 0. I now realize that the next 3 bits (12, 11, 10) are always 1.

    I seem to have some grounding issue or mis-understanding. I'm using a dual power supply, with V_A- connected to V_B+, to test the ADC. Should AIN+ and AIN- be relative to ground or relative to VCM? The voltage between ground and VCM is 0.6V. I see a VCM_EXTERNAL connection on the board, should I use it?

    I also found a small error in document UG-490. JP7 connects by default B to center and not A to center as is written in table 1.

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