AD7960 : data set up / hold times in ref design

In the docs for the AD7960 , is a set of Verilog / Xilinx reference files for how to interface to the AD7960.


Looking at the echoed clock version, as it seems the easiest, I can not see any timing constraints for the design.

It could be they are there, but I'd expect a UCF file for ISE, or an XDC file for vivado.

I run the design in simulation , and it runs, but the timing is 'ambiguous' .

Does anyone have a the numbers to type into Xilinx tools to ensure the AD7960 interface will work,